L. J. Caluwaerts

dblp:85/6179 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1983
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Parallel and multicore computing · 33% Processor architecture and microarchitecture · 31% Memory systems · 19%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
dataflow architecture
0.021983
Implementing Streams on a Data Flow Computer System With Paged Memory · ISCA 1983
A data flow architecture with a paged memory system · ISCA 1982
Parallel and multicore computing › parallel programming models › automatic parallelization
functional program parallelization
0.011983
Implementing Streams on a Data Flow Computer System With Paged Memory · ISCA 1983
Parallel and multicore computing
parallel programming models
0.011983
Implementing Streams on a Data Flow Computer System With Paged Memory · ISCA 1983
Distributed systems
stream processing
0.011983
Implementing Streams on a Data Flow Computer System With Paged Memory · ISCA 1983
Memory systems
memory management
0.011982
A data flow architecture with a paged memory system · ISCA 1982

Methods — techniques the papers use, named apart from their topics

data flow graph · 0.0pipelining · 0.0token labeling · 0.0
YearPublicationVenuePosition
1983 Implementing Streams on a Data Flow Computer System With Paged Memory
abstract
In several data flow architectures, “streams” are proposed as special data structures able to improve parallel execution in functional programs by providing a pipelining effect between different program parts.
L. J. Caluwaerts, J. Debacker, Jean A. Peperstraete
ISCA1
1982 A data flow architecture with a paged memory system
abstract
During the last ten years, data flow has become an exciting research area and several architectures have been proposed and built. They differ mostly in the way they handle data structures and how they provide mechanisms for token labeling or colouring in order to make data flow graphs reentrant. The paper presents a data flow architecture with a paged memory system to hold both data flow programs and data structures. The token labeling mechanism is coupled with the memory management system in order to provide for each token a unique memory location. The instruction format allows instructions with multiple operands and multiple destinations for each result. Data structures are held in memory while pointers to the structures are circulating as tokens. The proposed architecture is able to execute data flow programs at the level of single instructions or at a higher level.
L. J. Caluwaerts, J. Debacker, Jean A. Peperstraete
ISCA1