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Raju Joshi

dblp:85/7033 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 50% Reconfigurable computing and FPGAs · 22% Embedded and real-time systems · 22%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
design methodology		 0.011995
System Design Methodology of UltraSPARC-I · DAC 1995
Electronic design automation › hardware verification and test
hardware verification		 0.011995
UltraSPARC-I Emulation · DAC 1995
Embedded and real-time systems › embedded system design
microprocessor-based system design		 0.011995
System Design Methodology of UltraSPARC-I · DAC 1995
Reconfigurable computing and FPGAs
processor emulation		 0.011995
UltraSPARC-I Emulation · DAC 1995
Electronic design automation
timing analysis		 0.011995
System Design Methodology of UltraSPARC-I · DAC 1995

Methods — techniques the papers use, named apart from their topics

timing analysis · 0.0noise analysis · 0.0emulation · 0.0
YearPublicationVenuePosition
1995 UltraSPARC-I Emulation
abstract
The next generation UltraSPARC-I CPU represents a significant step forward in processor performance at the cost of increased design complexity.Added complexity increases the risks in achieving functionally correct first silicon.Existing design verification techniques were supplemented by applying emulation to obtain an early look at functionality.Discussed are the goals, methods and results of the UltraSPARC-I emulation.
James Gateley, Miriam Blatt, Dennis Chen, Scott Cooke, Piyush Desai, Manjunath Doreswamy, Mark Elgood, Gary Feierbach, Tim Goldsbury, Dale Greenley, Raju Joshi, Mike Khosraviani, Robert Kwong, Manish Motwani, Chitresh Narasimhaiah, Sam J. Nicolino Jr., Tooru Ozeki, Gary Peterson, Chris Salzmann, Nasser Shayesteh, Jeffrey Whitman, Pak Wong
 DAC11
1995 System Design Methodology of UltraSPARC-I
abstract
Increasing complexity of microprocessor-based systems puts pressure on a product's time-to-market.We describe a methodology used in designing the system interface of UltraSPARC-I.This methodology allowed us to define the system interface architecture, verify the functionality, perform timing and noise analysis and do the physical board design in parallel.This concurrency permitted rapid implementation of the microprocessor and the system.
Lawrence Yang, David Gao 0001, Jamshid Mostoufi, Raju Joshi, Paul Loewenstein
 DAC4