This paper presents a low-power, optical systemon-chip (SoC) enabling wireless fluorescence detection. The proposed SoC, in size of 2 × 2.7 mm2, integrates a high-sensitivity optical front-end, battery management unit and energy harvesting, and a wireless data transceiver. A fast-settling transimpedance amplifier (TIA) ensures rapid startup and minimizes power consumption, supported by dual-mode low dropout regulators (LDO regulators) for efficient power management. The SoC achieves ultra-low power, 1 μW, operation with 0.5 pA sensitivity, suitable for non-invasive cellular monitoring. The SoC is implemented using 65 nm CMOS technology.

A parallel-path amplifier (PPA) incorporating a switched-based slew rate and gain boosting stage as a feed-forward path, in parallel with a linear amplifier is introduced in this brief as an alternative to conventional analog amplifiers to achieve a high accuracy through the linear path and high slewing through the assisted feed-forward path. The feed-forward path employs a pre-amplifier, hysteresis-detector, and differential charge pumps, while the linear path includes a recycling folded-cascode amplifier. An analysis is performed to study the amplifier’s settling error with and without the feed-forward path, and also the trade-off between the dead-zone width of the hysteresis detector and the amplifier’s settling speed. The assisted feed-forward path has improved the slew rate$\times 2.5$–800 V/$\mu $s, effective GBW by 15%, and dc gain by 16 dB at the expense of adding$187.5~\mu $A extra current consumption and$1.25~\mu $m2extra silicon area. To prove the concept, the proposed amplifier is used as a multiplying digital-to-analog converter (MDAC) amplifier of an 8-bit pipeline analog-to-digital converter (ADC), and the ADC is fabricated in a 65-nm CMOS process. The results reveal that the spurious free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) performances are improved by 6–7 dB in the presence of the feed-forward path.

Non peer reviewed

This special section is composed of substantially extended handpicked papers from the IEEE Nordic Circuits and Systems Conference (NorCAS) 2022 that took place in October 2022 in Oslo, Norway.

A low-quiescent current output-capacitorless class-AB CMOS low-dropout voltage regulator (LDO) capable to source/sink current to/from the load is presented, which is suitable for hybrid or linear-assisted structures utilized in envelope elimination and restoration (EER) applications. The proposed LDO regulator is designed and characterized in 0.18 μm CMOS process to provide a 1 V stable output voltage with 200 mV dropout without any off-chip output capacitor and can deliver a current range of 160 mA between -80 mA and +80 mA to the load, while consumes only 1.8 μA quiescent current.

This paper presents an output-capacitorless class-AB low-dropout (LDO) regulator with load current sinking and sourcing ability. The proposed LDO consists of two complementary pass transistors, controlled using a level shifter technique. The transient improvement section applied to the gates of the pass devices enhances the transient performance of the LDO. The proposed LDO is designed in TSMC 0.18 μm CMOS process with input and output voltages of 1.2-2.5 V and 1 V, respectively, 10 pF output capacitor, and quiescent current of 3.14 μA, and is capable to sink and source maximum load currents of ±100 mA, giving the current efficiency of 99.99%.

This paper presents an output-capacitorless low-dropout (LDO) regulator based on improved flipped voltage follower power stage for use in power management circuits. A new error amplifier (EA) structure, named as gain-bandwidth enhanced EA, is embedded in the LDO regulator. The LDO regulator is designed for the input and output voltages of 1.2 V and 1 V, respectively. Fast transients, low overshoot and undershoot, and low quiescent current of 6 μΛ are achieved for the proposed circuit. The LDO regulator is designed for maximum load current of 50 mA, achieving the current and power efficiencies of 99.99% and 83.3%, respectively. Additionally, up to 131 pF capacitance is used in the proposed LDO structure. The proposed circuit is designed and verified in HSPICE in TSMC 0.18 μm mixed signal CMOS process.

In this paper, a new structure based on linear-assisted DC-DC buck converter principle is proposed. Using a new class-AB LDO regulator instead of the conventional linear one (based on a push-pull output stage) in the hybrid scheme, reduces the difference between input and output voltages and also the switching frequency of the buck converter. Thus, the proposal achieves higher power efficiency rather than the conventional linear-assisted converter, desired for power management systems of battery operated devices like biomedical implants and energy harvesting applications. In addition, the circuit provides a lower output ripple and better transient response. A comparison analysis is done with regards to the considered performance indexes between the proposed structure and linear-assisted buck converter, and the results are validated in HSPICE in a 0.35 μm CMOS process.

This paper deals with a circuit proposal along with theoretical analysis to provide a solution for enhancing the stability and transient performance of external capacitorless low-dropout regulators (CL-LDOs) by segmenting the pass transistor to smaller sizes. The stability and transient analysis is carried out on the CL-LDO with two different size-segmented pass transistors in comparison with the conventional CL-LDO with single large size pass device. The analysis shows that the pass transistor segmentation leads to better stability, i.e., greater phase margin especially at no-load and light-load conditions, wider bandwidth, and improved transient behavior, i.e., lower settling time and output voltage deviations due to the load transients. The aforementioned topologies are modeled and validated in HSPICE using a 0.35 μm CMOS process, and the results are in conformity with the analytical statements.

A low quiescent current output-capacitorless CMOS LDO regulator based on a high slew-rate current-mode transconductance amplifier (CTA) as an error amplifier is presented. Load transient characteristic of the proposed LDO is improved even at low quiescent currents, by using a local common-mode feedback (LCMFB) in the proposed CTA. This provides an increase in the order of transfer characteristic of the circuit, thereby enhancing the slew-rate at the gate of pass transistor. The proposed CTA-based LDO topology has been designed and post-layout simulated in HSPICE, in a 0.18 μm CMOS process to supply a load current between 0-100 mA. Postlayout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10-100 pF.

In this paper a fast transient response low-dropout regulator (LDO) based on a current feedback amplifier (CFA) is presented. The utilized CFA consists of an open-loop voltage follower with output local current-current feedback based on a level-shifted flipped voltage follower (LSFVF) to achieve high regulation and fast transient response. The inverting output buffer stage of the CFA together with current-mirror-based driving of the power pass transistor results in high PSRR. The circuit does not require any internal compensation capacitor and is stable for a wide range of output load currents 0-100 mA and a 1μF output capacitor. Post-layout simulation results for a 0.35μm CMOS process reveal that the maximum output voltage deviation of the proposed LDO for 0-100mA load transient with rise and fall times of 10 and 100ns is only 3mV, and the PSRR is smaller than -56dB over the entire load current range.