The 2021 International Symposium on Physical Design lifetime achievement award goes to Dr. Louis K. Scheffer for his outstand contributions to the field. This autobiography in Lou's own words provides a glimpse of what has happened through his career.

Many different physical substrates can support complex computation. This is particularly apparent when considering human made and biological systems that perform similar functions, such as visually guided navigation. In common, however, is the need for good physical design, as such designs are smaller, faster, lighter, and lower power, factors in both the jungle and the marketplace. Although the physical design of man-made systems is relatively well understood, the physical design of biological computation has remained murky due to a lack of detailed information on their construction. The recent EM (electron microscope) reconstruction of the central brain of the fruit fly now allows us to start to examine these issues. Here we look at the physical design of the fly brain, including such factors as fan-in and fanout, logic depth, division into physical compartments and how this affects electrical response, pin to computation ratios (Rent's rule), and other physical characteristics of at least one biological computation substrate. From this we speculate on how physical design algorithms might change if the target implementation was a biological neural network.

Our technical ability to collect data about biological systems far outpaces our ability to understand them. Historically, for example, we have had complete and explicit genomes for almost two decades, but we still have no idea what many genes do. More recently a similar situation has arisen, where we can reconstruct huge neural circuits, and/or watch them operate in the brain, but still don’t know how they work. This talk covers this second and newer problem, understanding neural circuits. We introduce a variety of computational tools currently being used to attack this data-rich, understanding-poor problems. Examples include dimensionality reduction for nonlinear systems, looking for known and proposed circuits, and using machine learning for parameter estimation. One general theme is the use of biological priors, to help fill in unknowns, see if proposed solutions are feasible, and more generally aid understanding.

Fruit flies (Drosophila melanogaster) are small insects, with correspondingly small power budgets. Despite this, they perform sophisticated neural computations in real time. Careful study of these insects is revealing how some of these circuits work. Insights from these systems might be helpful in designing other low power circuits.

Natural neural circuits, optimized by millions of years of evolution, are fast, low power, robust, and adapt in response to experience, all characteristics we would love to have in systems we ourselves design. Recently there have been enormous advances in understanding how neurons implement computations within the brain of living creatures. Can we use this new-found knowledge to create better artificial system? What lessons can we learn from the neurons themselves, that can help us create better neuromorphic circuits?

A central problem in neuroscience is reconstructing neuronal circuits on the synapse level. Due to a wide range of scales in brain architecture such reconstruction requires imaging that is both high-resolution and high-throughput. Existing electron microscopy (EM) techniques possess required resolution in the lateral plane and either high-throughput or high depth resolution but not both. Here, we exploit recent advances in unsupervised learning and signal processing to obtain high depth-resolution EM images computationally without sacrificing throughput. First, we show that the brain tissue can be represented as a sparse linear combination of localized basis functions that are learned using high-resolution datasets. We then develop compressive sensing-inspired techniques that can reconstruct the brain tissue from very few (typically five) tomographic views of each section. This enables tracing of neuronal processes and, hence, high throughput reconstruction of neural circuits on the level of individual synapses.

Electronic and biological systems both perform complex information processing, but they use very different techniques. Though electronics has the advantage in raw speed, biological systems have the edge in many other areas. They can be produced, and indeed self-reproduce, without expensive and finicky factories. They are tolerant of manufacturing defects, and learn and adapt for better performance. In many cases they can self-repair damage.

Future progress in neuroscience hinges on reconstruction of neuronal circuits to the level of individual synapses. Because of the specifics of neuronal architecture, imaging must be done with very high resolution and throughput. While Electron Microscopy (EM) achieves the required resolution in the transverse directions, its depth resolution is a severe limitation. Computed tomography (CT) may be used in conjunction with electron microscopy to improve the depth resolution, but this severely limits the throughput since several tens or hundreds of EM images need to be acquired. Here, we exploit recent advances in signal processing to obtain high depth resolution EM images computationally. First, we show that the brain tissue can be represented as sparse linear combination of local basis functions that are thin membrane-like structures oriented in various directions. We then develop reconstruction techniques inspired by compressive sensing that can reconstruct the brain tissue from very few (typically 5) tomographic views of each section. This enables tracing of neuronal connections across layers and, hence, high throughput reconstruction of neural circuits to the level of individual synapses.

It may seem premature to worry about the design of of living systems when we do not yet fully understand their operation. However, the path to understanding is clear, and design will inevitably follow. It's not too early to think about how this might be structured.

Static-timing analysis (STA) has been one of the most pervasive and successful analysis engines in the design of digital circuits for the last 20 years. However, in recent years, the increased loss of predictability in semiconductor devices has raised concern over the ability of STA to effectively model statistical variations. This has resulted in extensive research in the so-called statistical STA (SSTA), which marks a significant departure from the traditional STA framework. In this paper, we review the recent developments in SSTA. We first discuss its underlying models and assumptions, then survey the major approaches, and close by discussing its remaining key challenges.

This paper looks at the CAD implications of possible new interconnect technologies. We consider three technologies in particular: three dimensional ICs, carbon nanotubes as a replacement for metal interconnects, and optical interconnections for longer range on-chip communication. Each of these requires new CAD support to be used effectively.

The days when a router simply connected up the nets, obeying simple width and spacing rules, are long gone. While modern routers are still expected to connect things up correctly (albeit with a much more complex set of design rules), they are also expected to balance many more objectives. Even in a digital design, routers are now expected to preserve or enhance timing, get rid of crosstalk violations, even out metal density, insert redundant vias, minimize critical area, and generate 'litho friendly' geometry where possible, just to name a few additional tasks. Analog and mixed signal design adds many more, and more complex, constraints. Managing this large set of often conflicting objectives requires a router built for this express purpose. This talk will discuss Cadence's 'Space Based Router', a new router designed with DFM and DFY in mind.

Modern IC manufacturing processes are enormously complex. There are at least two possible approaches for dealing with this. On the one hand, we can come up with a relatively small number of specific structures that are known to work. This simplifies the design problem enormously, but limits, to at least some extent, what we can build. On the far extreme, we can model every step of the manufacturing process in gory detail. This allows a sufficiently motivated and intelligent designer to achieve the highest performance of which a process is capable, but at a huge cost in complexity. Many intermediate solutions are of course possible. Our panelists, as befits their varied backgrounds, will stake out different positions along the complexity-performance tradeoff, and argue that their position is the true sweet spot, where the bulk of IC design should be done.

Process variations - which affect critical electrical parameters and lead to both random and systematic changes in circuit performance - have always posed significant challenges to semiconductor design. In the past, within-die process variation was relatively small, and methods such as corner-based analysis were sufficient. This allowed timing analysis tools to calculate delays, slew times, coupling and power in a straightforward way. Today, the International Technology Roadmap for Semiconductors suggests that the semiconductor industry's historical ability to control process variations is under siege, for both devices and interconnects. As statistical variation increases, will corner-casing lead to too much conservatism, and hence a requirement for new statistical timing and noise analysis tools? In other words, is the design flow inevitably moving to "delay is no longer a number; it's a distribution"? Or are the urgency and the advantages of statistical timing analysis overstated.

One of the often-overlooked aspects of Moore's law is that it is predicated solely on device performance scaling linearly with dimension. Yet scaled interconnect performance has remained essentially constant. The physics of the problem is rather brutal; while capacitance drops with the reduced length of interconnect, its resistance rises and the RC time product is constant under uniform scaling, greatly lagging scaled device performance. In the late-eighties, one micron process dimensions had little wire resistance and the RC delay component of interconnect was negligible. But as process dimensions scaled below one-quarter micron in the late nineties, fears of interconnect delay dominance reached a fevered pitch in the physical design community. Speculation ran rampant that resistive interconnects would soon dominate the performance of design. We dub this era the Rise of the Interconnect Chicken Little.In 1998, Keutzer and Sylvester sought to dispel the hype associated with these wire-related problems, arguing that appropriate device sizing and use of design hierarchy would prevent significant exposure to RC delay in synthesis blocks of 50K gates or less. Their argument was supported by the then-prevalent wisdom that interconnect delay was not dominant and that sharp designers and process engineers could work their way around this problem. We'll dub this general consensus as the Interconnect Ostrich point of view. The following year, Ho and Horowitz attempted to reinvigorate the Chicken Little argument in a publication challenging the Keutzer/Sylvester viewpoint with yet more data on interconnect scaling, but this interconnect-debate-through-papers yielded little change-of-heart on either side. Many other deep-submicron issues have since captured the attention of the designer (e.g., coupling noise, IR drop, and MOSFET leakage) and the interconnect paper-debate generally faded to the background.Recently, however, projections of historical scaling trends by Saxena, et al, have predicted synthesis blocks with 70% (!) of their cell count dedicated to interconnect buffers within a few process generations, raising both skepticism and fearful reactions in the physical design community. While we might think of this as the Return of Chicken Little, the debate has grown far more complex: competition over wiring resources with power supply and clock, concern over noise, and the potential for degraded device performance due to leakage all cast their shadow over this issue. Some now argue we need to consider more exotic circuitry or even restrict our VLSI architectures dramatically. Rather than wait for this debate to rage on in future physical design publications, the time is now to have the Great Interconnect Debate, the subject of this panel.

Overview Two years ago, DAC-2001 attendees enjoyed a thrilling debatepanel, “Who’s Got Nanometer Design Under Control?”, pitting sky-is-falling Physics die-hards against not-to-worry Methodology gurus. Then, the DAC audience overwhelmingly voted the match for the Methodologists. Now, we've just gone through the biggest business downturn in the industry's history, and we're hearing more and more about chip failures due to 130nm physical effects. Both physics and economics are a lot worse than we thought two years ago. Where are those simple, correct-by-construction methodologies for signal integrity, power integrity, low-power, etc. that we were promised? Were we bamboozled by glib promises from those Methodologists? In this session, we bring back the panelists from two years ago, not for another debate, but to hear well-reasoned perspectives on how to prioritize spending to address nanometer design challenges. Yes, methodology can solve any problem – but now we want to know which problems, in what priority order, at what cost. The panel will address the following questions. • What are the economic impacts and significance of the key nanometer design challenges, relative to each other? • Which nanometer design problems merit responsible R&D investment, in what amounts and proportion? • What is the likelihood of success, both near-term and longterm, in solving key nanometer design challenges? • Where will the answers come from? To keep the discussion very concrete, each panelist will be given a $100 budget, and must defend their allocation of this budget to attack various design problems. Where should the $100 be spent? The audience will determine the best-reasoned allocation, and the winning panelist keeps all the money.

Before manufacturing, each chip design must be inspected for possible errors. For example, design rule checking is used to check for adherence to the physical manufacturing rules, and static timing analysis is used to verify that the design has adequate performance. Although modern chip designs are invariably specified hierarchically, verification algorithms can treat this hierarchy in different ways. The most straightforward way to verify a hierarchical design is to expand (or flatten) the hierarchy, then do the test. Since most verification algorithms involve at least sorting the data, such algorithms are at least O(N log N), where N is the size of the flattened hierarchy. Alternatively, a verification tool can try to use the hierarchy rather than flattening it. One form of hierarchical verification involves verifying each cell, generating a model (also called an abstract) for each cell, and then checking all interactions between cells by using their abstracts. Under some conditions, this may be more efficient than flattening the hierarchy and then verifying. In particular, if the size of the abstract is O(n/sup a/) for a cell containing n primitives, and the time to verify a cell and generate the abstract is O(n/sup b/), then the complete verification of all levels of the hierarchy is O(N), provided ab<1.

As processes shrink, gate delay improves much faster than the delay in long wires. Therefore, the long wires increasingly determine the maximum clock rate, and hence performance, of more and more chips. One solution to this problem is to pipeline the global interconnect, enabling the whole chip to run at the speed of local operations. While known to work well, this optimization is seldom used because of practical difficulties - it is hard to change the RTL, test vectors become invalid, and it's hard to prove correctness of any changes. Here we look at some ways these difficulties could be overcome.

As fabrication technology moves to 100 nm and below, profound nanometer effects become critical in developing silicon chips with hundreds of millions of transistors. Both EDA suppliers and system houses have been re- tooling, and new methodologies have been emerging. Will these efforts meet the challenges of nanometer silicon such as performance closure, power, reliability, manufacturability, and cost? Which aspects of nanometer design are, or are not, under control? This session will consist of a debate between two teams of distinguished representatives from EDA suppliers and system design houses. Which side has the right answers and roadmap? You and a panel of judges will decide!

We present a timing- and crosstalk-driven router for the chip assembly task that is applied between global and detailed routing. Our new approach aims to process the crosstalk and timing constraints by ordering nets and tuning wire spacing in a quantitative way. The new approach fits between global routing and detailed routing along the physical design flow. It is the first to address the timing- and crosstalk-driven area routing problem using crosspoint assignment prior to the detailed routing stage, in contrast to the most previous approaches applied in the post-detailed routing stage. Our new approach enjoys a larger optimization solution space than the previous approaches whose solution space is highly limited by routed geometric constraints. Based on the global routing information, our graph-based optimizer preroutes wires on the global routing grids incrementally. The graph-based optimizer has two stages, net order assignment and space relaxation. A quick capacitance extraction and Elmore delay calculator considering signal switching activities are implemented to find the timing of critical nets and to provide the timing slack database of critical nets. As the graph-based algorithm proceeds, the path delay of critical nets and the timing slack database are updated. During the optimization process, it only optimizes the timing critical paths with negative slack values. The experimental results show a 5%-16% delay reduction for MCNC macrocell benchmark circuits for a 0.25 /spl mu/m process for wire geometric ratio (height/width)=1.0, against a 25% delay reduction if there is infinite space around each metal wire on the same layer.

It's been one year since Richard Goering told us that the EDA RTL-to-GDSII world was about to change. What have we learned? Who's winning, and who's not? This panel, consisting of the leading large and upcoming players in this space, will deliver concrete data to differentiate leading approaches to achieving design closure. Does the solution lie in raw speed and RTL optimization, with the synthesis-place-route back end just a commodity? Does the solution lie in new metrics for design convergence, and symmetric multiprocessing platforms for efficiency? Does the solution lie in a holistic, unified architecture of data model and tools? Or does the solution lie in extensions and unifications of existing production-proven logic, timing, and layout optimization technologies? A hard-hitting panel session will reveal the answers!

We present a timing and crosstalk driven router for the chip assembly task that is applied between global and detailed routing. Our new approach aims to process the crosstalk and timing constraints by ordering nets and tuning wire spacing in a quantitative way. Our graph-based optimizer preroutes wires on the global routing grids incrementally in two stages - net order assignment and space relaxation. The timing delay of each critical path is calculated taking into account interconnect coupling capacitance. The objective is to reduce the delays of critical nets with negative timing slack values, by tuning net ordering and adding extra wire spacing. It shows a remarkable 8.4-25% delay reduction for MCNC benchmarks for wire geometric ratio=2.0, against a 33% delay reduction if interconnect interference disappear.

Correct interconnectdesign is crucial to making sub-micron chips that work.Right now CAD tools do little or nothing to help prevent signal integrity and reliability problems in the interconnect.However, they need to address this problem very soon since a significant percentage of the nets in a 0.25 micron process will be affected by one or more signal integrity problems.These must be fixed automatically, since there will be too many to be fixed by hand.This paper looks at some possible solutions to thii problem.There are two basic ways to attack this problem -methodology changes and CAD tool changes.Neither is likely to solve the problem alone, and an optimum solution will include some of each.This paper concentrates on the CAD tool changes needed to automatically address sub-micron interconnect issues.A large number of tools in the design flow must be changed, and the data flow between these tools will be considerably more complex than in existing flows.1.

Hierarchical DRC and component extract offer many advantages but no one form of hierarchical analysis fits all situations. This paper introduces hierarchical analysis in which the user specifies how abstract representations of cells are formed, how they are checked, and what to do if a violation is detected. This allows one analysis program (with different rules) to use the designer's hierarchy for a wide variety of different analyses. In particular, analyses that had been difficult in previous schemes (cross coupling capacitances, terminals in the center of cells, multilayer interconnects) can now be handled hierarchically. Topics: 2,5,7