This paper presents 128 × 128 pixel CMOS event camera front-end and its ADC that can produce multi-bit temporal difference events from subsequent pixel intensity values. The implementation was done with 180 nm CMOS technology. The designs of the pixel front-end, column ADC, FPN compensation, as well as their simulation and measurement results, are presented. Our implementation uses temporal events to construct a grayscale frame without the need to a full range ADC. This approach provides a means to have pixel grayscale values that are in sync with temporal difference events, wherein having access to both grayscale information and temporal difference events could be useful in further processing steps that are needed in applications such as moving object detection and classification.

HDR imaging is a technique that allows much larger range of luminosity to be expressed than the image sensor is able to capture. One way to acquire HDR images is to combine multiple low-dynamic-range images, taken with different exposure times, into one image that can express the larger dynamic range. For real-time imaging, digital pixels utilizing self-reset ADCs have made HDR imaging possible in hardware level. In this paper we propose a hardware circuit arrangement for constructing HDR images from low bit count samples captured from multiple frames.

In this paper we consider using memristors for high-dimensional computing that requires very large associative memories, but generally has good tolerance to nonidealities in the implementation medium. To consider such computing with existing devices, we present measurements of a tantalum oxide memristor that can be programmed to resistance values between high resistance state and low resistance state. Based on the measurements, we estimate the variation in the resistance states, and describe how a pseudo-analog programming operation can be used for trimming ON-resistance values. Finally, we discuss how different memory initialization and programming approaches affect the reliability of an associative search.

We recently mapped an algorithm for online learning of linear subspaces using local learning rules to an analog array computing framework. In this work we consider a simplified version of this algorithm which can be realized as a mixed-mode computing array. This allows similar learning results as the unmodified algorithm and is designed to allow large-scale test circuit fabrication with commercially available technologies. We demonstrate by numerical simulations of the mixed mode learning system that less than ten-bit resolution in the considered digital circuitry is sufficient for useful learning; such resolution allows efficient implementation of the related analog computations. The presented circuit has practical applications e.g. in signal classification, adaptive compression, and compressive sensing in low-power devices.

Summary form only given. The Von Neumann bottleneck originates from the low bandwidth between processing and memory. One paradigm that could ease the bottleneck is Computing-in-Memory (CiM), where the same elements store logic values and perform logical operations on them in the same physical location. Here, presented are implementations of the K-means clustering algorithm on a Memristive Logic Array-based CiM implementation and a Machine Learning specific Transport-Triggered Architecture (TTA) processor implemented on 28nm FDSOI technology and operating at 0.35V. While running K-means, the Memristive CiM is 5,7 times faster and uses 2,3 times less energy than the TTA processor. However, the average power consumption of the MLA is 2,5 times the power of the TTA.

The primary aim of this work is to provide new tools for machine learning and reasoning within a framework of computing with holistic data representations. Specifically, we demonstrate recursive construction of mappings and functions in high-dimensional computing with random vectors - a connectionist computing model which provides benefits similar to neural networks, but allows compositional learning. The computational operations considered in this work are applicable in learning by generalizing from small sets of example data. We demonstrate their use by constructing a simple reasoning model which learns modulo 10 addition and subtraction from a minimal set of examples. Finally, we give examples on how the presented computational operations can be used to compose and manipulate more complex structures in computing with high-dimensional random vectors.

We describe how an analog associative memory architecture can be used to infer time-variant states of a hidden Markov model (HMM), demonstrating computation of forward probabilities, backward probabilities, smoothing, and the Viterbi algorithm. This type of computing is well suited for implementation in array computing architectures, and the necessary elementary computations have been demonstrated in previous work. We consider the effect of limited accuracy in storage and computing elements on the inference reliability, and demonstrate that although the computation is iterative, reliable operation is not significantly affected by error accumulation.

Distributed associative memory architectures store data in multiple locations redundantly, and are thus robust to circuit irregularities and noise. In this paper we explain ways to store the occurrence statistics of vectors in a distributed memory. Sparse data vectors are used to maximize vector capacity, and binding of sparse vectors is used to combine elementary symbols into symbols that represent larger entities. The use of such statistics is demonstrated with an on-line learning example that uses redundancy reduction. We show that occurrence statistics can be represented with distributed Willshaw-type associative memories sing hardware counters, as well as symbolically using two-bit memory cells.

In this paper we present a CMOS implementation of a 512×512-cell Associative Content Addressable Memory (ACAM) in 180 nm CMOS. The memory can be operated either as an associative CAM or it can be configured into a Willshaw memory for operating with sparse data. The vector matching operation can use a tunable hit threshold or the strongest hit can be selected with a winner-take-all (WTA) network. Built-in row and column circuitry can perform logic operations on the contents of the row and column memories. The operation of the circuit is verified experimentally with an example on computing with random vectors.

In this work we consider the implementation of nondeterministic finite automata in autoassociative memory, and demonstrate mapping and operating such automata in an associative content-addressable/Willshaw-type memory circuit presented in a companion paper. This topic is relevant in the broader scope of in-memory computing, and offers a simple, flexible, and computationally efficient way of implementing nondeterministic finite automata using existing general-purpose associative memory hardware.

This paper presents the implementation of optical seam tracking for a laser welding process with parallel image processing on a smart camera. Real-time extraction of the seam location and direction is enabled by a combination of massively parallel focal plane processing on a Vision Chip and Hough-transform based analysis on an FPGA. The implementation of all analysis within a single embedded camera system offers low-lag control for correcting the path of a welding robot. The vision chip provides illumination adaptive image sensing and neighborhood based feature segmentation. To extract the dominant line from the segmented data, an auxiliary FPGA processor performs Hough analysis on the reduced binary data from the vision chip. The system can achieve a line extraction speed of more than 1000 fps, which enables real-time visual seam tracking and robot control. Evaluation results from on-line laser welding tests with processing performed on the camera system are reported in the article.

This paper presents the development of methods for real-time fine-tuning of a high power laser welding process of thick steel by using a compact smart camera system. When performing welding in butt-joint configuration, the laser beam’s location needs to be adjusted exactly according to the seam line in order to allow the injected energy to be absorbed uniformly into both steel sheets. In this paper, on-line extraction of seam parameters is targeted by taking advantage of a combination of dynamic image intensity compression, image segmentation with a focal-plane processor ASIC, and Hough transform on an associated FPGA. Additional filtering of Hough line candidates based on temporal windowing is further applied to reduce unrealistic frame-to-frame tracking variations. The proposed methods are implemented in Matlab by using image data captured with adaptive integration time. The simulations are performed in a hardware oriented way to allow real-time implementation of the algorithms on the smart camera system.

We show a Field-Programmable Analog Array complemented with post-processed memristors (FPAA/memristor hybrid circuit), and present it as a platform for analog signal processing. The FPAA is fabricated on CMOS and uses floating-gate transistors (FGT) to realize programmable wiring fabrics and analog computing resources. The memristors, post-processed on top of the FPAA, are analog, which means that their conductance can be programmed in a continuous fashion. We highlight the key differences between FGTs and memristors, and discuss how analog signal processing tasks could be divided between them. Experimental results of the FPAA-memristor hybrid circuit are presented.

Associative memories, in contrast to conventional address-based memories, are inherently fault-tolerant and allow retrieval of data based on partial search information. This paper considers the possibility of implementing large-scale associative memories through memristive devices jointly with CMOS circuitry. An advantage of a memristive associative memory is that the memory elements are located physically above the CMOS layer, which yields more die area for the processing elements realized in CMOS. This allows for high-capacity memories even while using an older CMOS technology, as the capacity of the memory depends more on the feature size of the memristive crossbar than on that of the CMOS components. In this paper, we propose the memristive implementations, and present simulations and error analysis of the autoassociative content-addressable memory, the Willshaw memory, and the sparse distributed memory. Furthermore, we present a CMOS cell that can be used to implement the proposed memory architectures.

This paper describes how memristors, together with CMOS transistors (CMOS-memristor hybrids), could be used for analog arithmetic within cellular (locally connected, regular) computing arrays, i.e., cellular nanoscale networks (CNN). Elementary analog programming of memristors and copying memristance values are described. Also, we show how memristors could be used for addition, subtraction, multiplication and division. Furthermore, we demonstrate how a local memristive computing unit could be mapped into a CNN cell. Relevant memristor models are shown and key simulations are presented.

We propose three new synthesis methods for memristive implication logic and compare these with each other and with a basic method which was originally proposed in [5]. The results show that by using complementary representation of variables and multi-input operation, the lengths of computational sequences required for computing a given Boolean function are significantly reduced; for the three-input parity function this reduction is approximately 85 percent compared to the basic method.

We determine an explicit procedure for representing any Boolean expression in a recursive form which can be realized using memristive devices, and demonstrate how the truth value of any Boolean expression can be determined using no more than two computing memristive devices. We present an algorithm which can be used to significantly reduce the number of implications required for representing a specific Boolean expression, and consider device-specific benefits in terms of reducing the lengths of computational sequences.

We describe a generic exponential model with four parameters for thin-film memristive devices. This model is used to analyze the time dependency of the threshold voltage which defines the transition between non-programming and programming phases of the device. A relationship between timescale of operation and threshold voltage is derived. Furthermore, self-terminating programming is considered using the results of this analysis. Finally, the effect of parameter variations on the threshold voltage is analyzed.

Emerging 3D-integration enables integrating high quality image sensors with various massively parallel processing elements. Analog motion estimation is one potential application, which is likely to result in significant benefits in the form of low power or high frame-rate 3D-integrated image sensor-processors. The system-level operation of a proposed analog motion estimation array, enabling all various block sizes from 4×4 to 16×16 is examined. The analog motion estimation circuitry has been designed as a 32×32 test array in 0.13 μm CMOS technology. The transistor-level simulation results combined with H.264/AVC JM 14.2 show equivalent rate-distortion results with SAD as the error measure and an approximately 7% increase in bitrate with a slight increase in image quality for SSE.

This paper describes a cellular nanoscale network cell structure that is aimed to be built as a CMOS-nanomemristor hybrid. The processing cell uses memristors as ON-OFF programmable synapses, local logic and memory. Local logic is based on memristor computations using material implication. Only 15 CMOS transistors per cell are used, independent of the size of the neighborhood, since memristors are used as synapses. Also, space-dependent templates (weight matrices) are possible at no extra hardware cost. The operation of the cell is described and simulation results are shown to illustrate the operation.

In this paper, a novel approach to computing arbitrary Boolean functions using a binary-state cellular neural/nonlinear/nanoscale network (CNN) architecture with local static memory is presented. We define explicitly how to map a given Boolean function and its input values to the cells of a specific type of binary CNN, and the global rules used to perform parallel calculations. Each of the computation steps can be performed asynchronously. Additionally, the total CNN area is readily split into subsections, each of which perform individual computations of different Boolean functions. The main benefits of our approach are simple implementation of arbitrary Boolean functions, built-in parallelism both in local and global scale of the computation and the possibility for asynchronous operation.

In this paper, we present a Spiking Neural Network (SNN) architecture that incorporates Integrate-and-fire (IF) type neurons and floating-gate transistors (FGTs) to store the synaptic weights. Compactness of the network has been the major target throughout the design. We believe that a CrossNet architecture lends itself very well to satisfy this goal. The synaptic weights are updated locally according to an approximation of Spike-Timing-Dependent Plasticity (STDP) rule. While the computations are performed internally in the analog domain the network is interfaced with a digital Address-Event-Representation (AER) to achieve robust off-chip communication. The operation of the array is described and selected simulations with 65 nm CMOS are shown.

This live demonstration and the accompanying full-length paper are related to the ISCAS track "cellular neural networks and array computing/implementations of topographical microprocessors".

This paper presents the MIPA4k, a 64times64 cell mixed-mode image processor array chip. The processor cell includes an image sensor, A/D/A conversion, embedded digital and analog memories and hardware-optimized grayscale and binary processing cores. This paper presents the architecture of the processor cell and the different functional hardware. The processor has been manufactured in a 0.13 micron CMOS technology and the chip size is 5.1times4.5 mm2with a cell area of 72times61 mum2.

In this paper we describe how the location and size of an object in a multi-object scene can be identified and classified using a processor array with a scalable region of interest. Objects of interest can be classified by matching them with 25-pixel object prototypes in a window that is adjustable from 17 x 17 to 5 x 5. Matlab simulations of the algorithms are shown. In order to carry out the operations effectively, the processor is equipped with a global OR and global sum. Also, the outputs of the row and column decoders can be determined by boundary cell outputs, in addition to the address bits. A 64 x 64-cell array has been sent to fabrication.

In this paper, a micropower CMOS voltage, current, and temperature reference fabricated in a 0.13μm CMOS process is presented. This bandgap-based circuit provides all reference voltages and currents, and temperature information for a low-power interface of a three-axis capacitive microaccelerometer. The total measured current consumption including all required reference voltage buffers, current mirrors, and scaling circuitry is 23.1μA. The simulated current consumption of the core circuit is 5.5μA. According to system measurements, the required resolutions, 10 bits for the reference voltages and 9 bits for the temperature reference, are achieved. The measured TC for the voltage reference is 9.9ppm/°C, and the analog output of the temperature reference is linear with a 4.9mV/°C slope.

In this paper, we present a novel massively parallel implementation of a local binary pattern based face recognition algorithm, improving the recognition accuracy. An adaptive block matching method is introduced in the context of the proposed algorithm for massively parallel image processing, allowing simultaneous face alignment and recognition. We also consider main architecture level issues in the hardware implementation of a dedicated binary array performing the LBP based face recognition

In this paper we analyze the reliability of computation of binary-programmable cellular nonlinear networks for processing binary data. We describe the probability of a cell producing an error with given inputs and the error probability when processing random data. Furthermore, we show how the error probability could be defined in case the cell needs to work correctly with all possible input combinations. This error probability is found by performing Monte Carlo simulations

In this paper, we present an effective mismatch compensation method for analog current mode processing. Such a method is required in current and future mixed-mode processing systems, which take advantage of analog processing in addition to conventional digital logic. The proposed design utilizes analog processing devices that can be scaled down with the manufacturing process, therefore employing the advantages of CMOS technology in the form of a smaller implementation area. The range of input currents employed is 1 /spl mu/A to 10 /spl mu/A. The example circuit can be calibrated within 1 % of the nominal value at the 4/spl sigma/ confidence interval with 65 /spl mu/m/sup 2/ of implementation area in 0.15/spl mu/m CMOS technology.

In this paper, measurement results for a micropower 2 MHz CMOS frequency reference circuit fabricated with a 0.13 mum CMOS process are presented. This frequency reference circuit, based on source-coupled CMOS multivibrator, provides the clock signal for a read-out circuit of a capacitive sensor. In addition to low power consumption, good frequency stability is required. Supply independent biasing and symmetrical loads are used to optimize the frequency stability. The typical power consumption is 3.0 muW at room temperature with 1.8 V supply voltage. When properly calibrated, the frequency stays within plusmn2.5% of the nominal oscillation frequency in the operating voltage range of 1.8-2.5 V (with plusmn10% variation) over a temperature range from -35 to +85 degC. The measured phase noise and jitter agree well with the simulations

This paper presents the measurement results for an analog to digital converter (ADC), which is targeted to operate especially in a video encoding system. It is designed to convert the dc coefficients of a current-mode discrete cosine transform into digital form. The converter is able to change its quantization factor adaptively, fulfilling the demands of several video compression standards. The maximum conversion resolution is 7frac12 bits. The measurements verify correct operation of the converter in terms of input-output behaviour and adaptivity of the quantization

In this paper we propose a method for reducing the length of the feature vectors in the local binary pattern (LBP) based face recognition. This is done to speed up the matching of the feature vectors in real-time face recognition and detection systems. We define a new discrimination concept of the uniform local binary patterns called symmetry. Patterns are assigned different levels of symmetry based on the number of ones or zeros they contain. These symmetry levels are rotation invariant allowing a general discrimination methodology. Empirical studies on both human perception and LBP face recognition accuracy using the standard FERET database confirm that the concept of symmetry is an efficient discriminator.

In this paper a design method for building high speed array computers on a single chip is demonstrated with two example realizations. The key idea in the method is that an array computer can be built using reusable, relatively simple building blocks. All necessary memory is distributed among processing units. The number of processing units in the array computer is selected based on speed requirements, yielding a low power, small die area realization. Two different measured array processor realizations designed using the method are depicted.

In this paper realization of couplings between cells in a polynomial type mixed-mode cellular neural network (CNN) is analyzed. The choice of the multiplier is discussed and two multiplier types are analyzed. Also, two circuits for generating the second and third order polynomial terms of cell output are described. The accuracy of the multipliers and polynomial circuits at the presence of device mismatch is analyzed.

In this paper the design issues of large globally connected compact neural networks are targeted. Building blocks of a cell that is capable of performing the hardware annealing function are designed. Different offset compensation schemes are used to eliminate the offset currents. The cell is designed to have voltage outputs to facilitate the interconnecting of cells. The blocks are processed with a 0.5 /spl mu/m standard digital CMOS process and measurement results of selected building blocks of the cell are included.