This paper demonstrates the design process and performance prediction of a cryogenic 22 nm FDSOI circuit using a design-oriented model. The simplified EKV model is adopted to capture IV characteristics of short-channel transistors, for which parameters are extracted from cryogenic measurement of commercial FDSOI MOSFETs. When applied to a complete circuit, the model accurately predicts performances at various back-gate voltages and temperatures, achieving less than 1 % average absolute error. This validates the presented analytical approach, even under the stringent requirements of low-temperature operation, paving the way to exploiting rather than enduring cryogenic temperature effects on CMOS designs.

The output conductance and transconductance are key small-signal parameters that typically set the dc gain of amplifiers. Although the transconductance can be modelled simply and accurately, modeling the output conductance over a large range of bias and geometries is much more challenging. In advanced technologies the self-gain has shrunk dramatically, while the transit frequency has increased significantly. The de-signer can hence choose a transistor length longer than minimal achieving a higher dc gain while still meeting the frequency specifications. Now, how much longer than minimum should he choose? We will try to answer this question by proposing a simple output conductance model that is valid over a wide range of bias and geometries. The model is validated by simulations for a 28-nm FDSOI CMOS process.

Energy efficiency is of utmost importance in modern applications. Power consumption optimisation could be improved by a comprehensive analytical modeling of the characteristics of critical blocks in a system. Dynamic range (DR) has a strong effect on the power consumption of analog circuits, and is determined by circuit non-linearity and noise level. Noise is well modelled even in deep sub-micron technologies, yet there is a lack of analysis and modeling of the non-linearity. An analytical MOSFET differential pair non-linearity model is presented in this work. The proposed model is universal to a wide range of technologies from long to ultra-deep sub-micron devices, and is valid for all operating regions as it is based on the EKV MOSFET model. Furthermore, a model including drain-voltage-induced non-linearity is also developed, and a concise 3dB input intercept point (IIP3) formula incorporating the drain induced non-linearity in terms of the voltage gain is presented. The proposed models are validated with DC and AC simulations and measurements.

The$G_{m}/I_{D}$approach has proven to be an efficient technique for the design of low-power analog circuits even in advanced technology nodes. It has already been shown that the normalized$G_{m}/I_{D}$is actually a universal figure-of-merit (FoM) that is independent of technology and of device geometry. In addition, we will show experimentally in this paper that the normalized$G_{m}/I_{D}$is also almost independent of temperature even down to cryogenic temperatures. Analog designers are currently struggling to design circuits that have to operate at cryogenic temperatures for quantum computing application. This is because the compact models available in the physical design kit (PDK) provided by foundries fail at cryogenic temperatures. While the models need to be improved to account for low-temperature physics, the$G_{m}/I_{D}$approach can help designing cryo-CMOS analog circuits. In this paper we will show how it can be used for the design of a simple low-noise amplifier in a 16 nm FinFET technology taking advantage of the temperature independence of$G_{m}/I_{D}$.

This paper establishes the close relation that exists between the Fano noise suppression factor$F$and the$G_{m}/I_{D}$FoM showing that$F$is proportional to the product of the thermal noise excess factor$\gamma_{n}$and the normalized$G_{m}/I_{D}$function. Taking advantage of the EKV model formulation of the normalized$G_{m}/I_{D}$and$\gamma_{n}$in terms of the inversion coefficient$IC$, a simple expression of$F$versus$IC$for long and short channel transistors is derived. The proposed model of$F$versus$IC$for short-channel devices is validated against measurement from various CMOS technologies. Additional measurements of$G_{m}/I_{D}$performed on FDSOI devices down to cryogenic temperatures show that it is a universal FoM almost independent of temperature. Since$F$is proportional to$G_{m}/I_{D},\ F$should also be almost temperature independent. The proposed model constitutes a good starting point for having a model of the MOSFET white noise that is valid in all regions of operation and down to cryogenic temperatures.

The$G_{m}/I_{D}$approach has proven to be an efficient technique for the design of low-power analog circuits. Until now it was mostly demonstrated on older CMOS technology nodes. In this paper we will show that the$G_{m}/I_{D}$methodology still holds for advanced technologies using the simplified EKV model which only requires 4 parameters for bulk and 5 for FDSOI. We will start with a brief presentation of the simplified EKV model highlighting how the normalization process can strip-off most of the technology dependence. Then we will introduce the concept of inversion coefficient$IC$and show that the normalized$G_{m}/I_{D}$only depends on$IC$and a parameter$\lambda_{c}$accounting for velocity saturation. Then we will show how to extract the few parameters needed from data either generated from the PDK or from measurements. We then will illustrate the methodology by a design example of an OTA in a 22nm FDSOI technology. The design is then validated by simulations using the founder PDK using the full BSIM-IMG compact model demonstrating an excellent agreement between the simulation results and the specifications despite the simplicity of the model and the methodology.

With rapid development of Internet of Things, there is high demand for miniaturized biochemical sensors, which enable a digital-controlled connection and portable integration. In this work, we report an ASIC interface for capacitive micromachined ultrasonic transducers (CMUTs), offering multi-channel monitoring of frequency shifts and supplying high-voltage (HV) source. Previously reported CMUTs-based biochemical sensors required a peripheral power source to provide a DC driving voltage (e.g.,10-50 V), which was higher than the common circuit supply (e.g., 1.2-5 V). This resulted in additional circuit footprints and parasitic effects, especially for high frequency. Instead, we proposed an ASIC interface designed through TSMC $0.18-\mu{m}$ HV BCD process with a die size of 2×2 mm2. Four-channel oscillators are proposed to track frequency shifts of CMUT resonators with a resonant frequency of 1.8MHz, and a start-up period up to $100\mu$ s and a phase noise of −38.73dBc/Hz at low offset of 100 Hz were observed, while consuming an average total power of $142.12\mu\mathrm{W}$ in continuous mode. A PMOS-based HV charge pump is presented to generate a voltage boosting of ~50 V with a 1.8-V input source, which enables tuning clock signals by implementing four-parallel ring oscillators with the frequency of 20-50 MHz. The proposed ASIC integrated with CMUTs is a molecules.

This paper presents an analysis of different modulations that can be used at low-IF in short-range frequency- modulated continuous wave (FMCW) radars which are more sensitive to DC offsets and flicker noise. These modulations are also a key functionality in multiple-input multiple-output (MIMO) FMCW radars to implement orthogonality between the different transmit signals. Architectures with two PLLs, set at slightly different frequencies to create a low-IF, and one PLL, using OOK and BPSK modulations, are compared regarding their phase noise at the resulting IF signal. Measurements were performed on a COTS 60 GHz FMCW radar to validate the calculated and simulated results.

In this paper a continuous-time low-pass analog filter based on the Cascoded Super Source Follower (C-SSF) architecture, implemented in a 28-nm bulk CMOS process, is presented. The target application is the transceiver analog baseband for the next-generation IEEE 802.11ax WiFi standard. To comply with the high-selectivity requirements, a 6th-order Chebyshev transfer function has been implemented as a cascade of three biquadratic cells. The high quality factors required by such topology have been achieved by cascoding the feedback transistor in the standard SSF cell, reducing the quality factor dependence on the output conductance of the source follower transistor. Designed with the Inversion-Coefficient (IC) methodology, the filter is able to operate for channel bandwidths ranging from 10 MHz to 20MHz by changing its bias current. Measurement results show that the filter has a minimum noise power of -55.1dBm and a maximum IIP3 of 14dBm consuming 49μW, i.e. 8.17μW per pole, occupying an area of 0.0099 mm2.

Worst-case design is used in IoT devices and high performance data centers to ensure reliability, leading to a power efficiency loss. Recently, approximate computing has been proposed to trade off accuracy for efficiency. In this paper, we use Inexact Speculative Adders, which redesign the adder architecture to shorten its critical path and improve performance, but introduces controlled structural errors. On the other hand, overclocking is used to reduce conservative timing guardbands but could normally introduce catastrophic timing errors, we thus apply a supervised learning model to overclock speculative adders and predict their timing errors. We build a methodology to combine both structural and timing errors and analyze how they interplay with each other to limit the overal errors.

This work explores the combination of a downscaled technology with in-pixel source-follower (SF) optimization, a high column-level gain and an analog implementation of Correlated-Multiple-Sampling (CMS) for noise reduction of CIS readout chains. Transient noise simulations show that in the optimal condition of a pMOS SF, a column-level gain equal to 64 and a CMS of order 8, the noise can be reduced to the extremely low value of 0.20e-rms, with a readout time of 43 μs, demonstrating the possibility of true photoelectron counting for this standard 65 nm process.

This paper carries out a power-driven performance analysis on the most widely used LC oscillators' topologies, by means of the Inversion Coefficient methodology. The aim is to investigate on the best trade-off for Internet-of-Things related applications, where power consumption shall be minimized. The analysis is based on the BSIM6 model targeting a 40nm CMOS technology to investigate the trade-offs related to each topology and comparing them with respect to output voltage amplitude, phase noise and power consumption. The comparison is based on a figure-of-merit highlighting the best biasing regions, in terms of Inversion Coefficient, for the target required performance.

Energy-efficiency is a critical concern for many systems, ranging from Internet of things objects and mobile devices to high-performance computers. Moreover, after 40 years of prosperity, Moore's law is starting to show its economic and technical limits. Noticing that many circuits are over-engineered and that many applications are error-resilient or require less precision than offered by the existing hardware, approximate computing has emerged as a potential solution to pursue improvements of digital circuits. In this regard, a technique to systematically tradeoff accuracy in exchange for area, power, and delay savings in digital circuits is proposed: gate-level pruning (GLP). A CAD tool is build and integrated into a standard digital flow to offer a wide range of cost-accuracy tradeoffs for any conventional design. The methodology is first demonstrated on adders, achieving up to 78% energy-delay-area reduction for 10% mean relative error. It is then detailed how this methodology can be applied on a more complex system composed of a multitude of arithmetic blocks and memory: the discrete cosine transform (DCT), which is a key building block for image and video processing applications. Even though arithmetic circuits represent less than 4% of the entire DCT area, it is shown that the GLP technique can lead to 21% energy-delay-area savings over the entire system for a reasonable image quality loss of 24 dB. This significant saving is achieved thanks to the pruned arithmetic circuits, which sets some nodes at constant values, enabling the synthesis tool to further simplify the circuit and memory.

This paper introduces an approximate adder architecture based on a digital quasi-feedback technique called Carry Cut-Back in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach prevents activation of the critical path, improving energy efficiency while guaranteeing low worst-case relative error. It offers a degree of freedom which allows to dissociate precision and dynamic range in fixed-point implementation. A design methodology is presented along with results and a comparative study. For a worst-case accuracy of 98%, energy savings up to 44% and power-delay-area reductions up to 62% are demonstrated compared to low-power conventional designs.

Inexact circuits and approximate computing have been gaining a lot of interest in order to improve performances and energy efficiency beyond the boundaries of conventional digital circuits. Image and video processing is one of the best candidate for applying such techniques. As one of the key building blocks, Discrete Cosine Transform (DCT) accelerators are investigated using pruned arithmetic circuits. A design methodology is presented in order to optimize both image quality and circuit performances. This work demonstrates that with such technique, savings are possible not only on arithmetic units, but in the entire accelerator hardware. Simulations show up to 12 % area and 10 % power savings with less than 20 dB PSNR degradation compared to the conventional DCT design.

Inexact and approximate circuit design is a promising approach to improve performance and energy efficiency in technology-scaled and low-power digital systems. Such strategy is suitable for error-tolerant applications involving perceptive or statistical outputs. This paper presents a novel architecture of an Inexact Speculative Adder with optimized hardware efficiency and advanced compensation technique with either error correction or error reduction. This general topology of speculative adders improves performance and enables precise accuracy control. A brief design methodology and comparative study of this speculative adder are also presented herein, demonstrating power savings up to 26 % and energy-delay-area reductions up to 60% at equivalent accuracy compared to the state-of-the-art.

A 2.4 GHz polar transmitter compliant with the IEEE 802.15.6 standard is presented in this paper. A Linearized class-C power amplifier, employing dynamic biasing is used to minimize the adjacent channel interference and satisfy the defined spectrum mask requirements. An FBAR based frequency synthesizer enables fast startup and channel switching times. It is capable of addressing all the channels within the MBAN and ISM bands (2.36–2.48 GHz). The transmitter was integrated in 65 nm CMOS technology. It provides 0 dBm of output power while drawing 8.7 mA of current from a 1.2 V supply. The standalone power amplifier exhibits peak efficiency of 16%.

Inexact or approximate circuits show great ability to reduce power consumption at the cost of occasional errors in comparison to their conventional counterparts. Even though the benefits of such circuits have been proven for many applications, they are not wide spread owing to the absence of a clear design methodology and the required CAD tools. In this regard, this paper presents a methodology to automatically generate inexact circuits starting from a conventional design by adding only one small step in the digital design flow. Further, this paper also demonstrates that achieving pruning at gate-level can lead to substantial savings in terms of power consumption, critical path delay and silicon area. An order of magnitude area and power savings is demonstrated for a 64-bit gate level pruned high-speed adder for a 10% relative error magnitude.

Energy wasted during the wake-up of radios significantly degrades the efficiency of duty-cycled Wireless Sensor Networks (WSN). The major contributor to this energy wastage is the PLL-based frequency synthesizer which has a long wakeup time. Furthermore, the rate of duty cycling in these radios is also constrained by the PLL which imposes an upper limit on the maximum data rate that can be achieved by the radio. In order to improve upon both these bottlenecks, this paper presents an overview of highly agile, PLL-free radios based on FBAR DCOs. These synthesizers have the advantage of a 5μs wakeup, thereby reducing the energy wastage. In addition, they also support high-data rates (upto 16 Mbps) thereby increasing the rate of duty cycling which also improves the energy efficiency. The extremely low phase noise of the FBAR is an added advantage that has been leveraged to provide a low power channel selection filter for a sub-sampling receiver architecture.

We present a zero hardware-overhead design approach called reciprocative error compensation (REC) that significantly enhances the energy-accuracy trade-off gains in inexact signal processing datapaths by using a two-pronged approach: (a) deliberately redesigning the basic arithmetic blocks to effectively compensate for each other's (expected) error through inexact logic minimization, and (b) "reshaping" the response waveforms of the systems being designed to further reduce any residual error. We apply REC to several DSP primitives such as the FFT and FIR filter blocks, and show that this approach delivers 2-3 orders of magnitude lower (expected) error and more than an order of magnitude lesser Signal-to-Noise Ratio (SNR) loss (in dB) over the previously proposed inexact design techniques, while yielding similar energy gains. Post-layout comparisons in the 65nm process technology show that our REC approach achieves upto 73% energy savings (with corresponding delay and area savings of upto 16% and 62% respectively) when compared to an existing exact DSP implementation while trading a relatively small loss in SNR of less than 1.5 dB.

The domain of inexact circuit design, in which accuracy of the circuit can be exchanged for substantial cost (energy, delay, and/or area) savings, has been gathering increasing prominence of late owing to a growing desire for reducing energy consumption of the systems, particularly in the domain of embedded and (portable) multimedia applications. Most of the previous approaches to realizing inexact circuits relied on scaling of circuit parameters (such as supply voltage) taking advantage of an application’s error tolerance to achieve the cost and accuracy trade-offs, thus suffering from acute drawbacks of considerable implementation overheads that significantly reduced the gains. In this article, two novel design approaches called Probabilistic Pruning and Probabilistic Logic Minimization are proposed to realize inexact circuits with zero hardware overhead.Extensive simulations on various architectures of critical datapath elements demonstrate that each of the techniques can independently achieve normalized gains as large as 2x--9.5x in energy-delay-area product for relative error magnitude as low as 10 − 4% --8% compared to corresponding conventional correct circuits.

This paper presents a front-end circuit for electrochemical biosensors used in applications like DNA sensing. Novelty in this work lies in the front-end architecture which uses noise canceling (NC) combined with chopper stabilization (CS) for rejecting 1/f noise and to our knowledge, a front-end using the principle of noise canceling for 1/f noise rejection has not been reported. Motivation for using this front-end are: 1) The circuit exhibits low noise performance with its sensitivity not being limited by 1/f noise thanks to noise canceling and chopping. 2) The canceling property in this topology is used effectively to achieve improved linearity and higher dynamic range (DR) in addition to 1/f noise rejection. The fully differential front-end circuit is designed in 0.18 μm CMOS process and consumes 46 μA while operating on 1.8 V supply voltage. Based on the simulation results, a DR improvement of greater than 10 dB is achieved by the use of canceling technique.

In this work, a sub sampling receiver front end at 2.4 GHz with high Q filtering to perform channel selection at RF is presented. A low power solution for channel selection directly at RF is proposed in this work using “pseudo-self-biased” inverter amplifier with a BAW resonator lattice as a load to realize high selectivity. This work focusses on the Bluetooth LE standard, however the front-end can be used for any protocol standards for radios working at 2.4 GHz. A low power BAW based digitally controlled oscillator (DCO) is used as a reference to a LC PLL to perform channel selection. An integer divided version of the BAW DCO signal is used as clock for the sub-sampler to down-convert the selected channel from “super-high IF” to baseband in quadrature. The proposed architecture is designed in 0.18µm CMOS process and validated using ELDO-RF simulations.

Inexact Circuits or circuits in which the accuracy of the output can be traded for energy or delay savings, have been receiving increasing attention of late due to invariable inaccuracies in designs as Moore's law approaches the low nanometer range, and a concomitant growing desire for ultra low energy systems. In this paper, we present a novel design-level technique called probabilistic pruning to realize inexact circuits. Unlike the previous techniques in literature which relied mostly on some form of scaling of operational parameters such as the supply voltage (Vdd) to achieve energy and accuracy tradeoffs, our technique uses pruning of portions of circuits having a lower probability of being active, as the basis for performing architectural modifications resulting in significant savings in energy, delay and area. Our approach yields more savings when compared to any of the conventional voltage scaling schemes, for similar error values. Extensive simulations using this pruning technique in a novel logic synthesis based CAD framework on various architectures of 64-bit adders demonstrate that normalized gains as great as 2X-7.5X in the Energy-Delay-Area product can be obtained, with a relative error percentage as low as 10-6% up to 10%, when compared to corresponding conventionally correct designs.

Recognizing the importance of interfacing a variety of sensors and networking such sensors around the body area and by cellular services, a Swiss project within the Nano-Tera.ch Initiative is dedicated to developing a platform of circuit technologies for medical data acquisition and communication.

This paper explores the use of MEMS devices such as bulk acoustic wave (BAW) and low frequency silicon resonators, in combination with digital circuits and techniques, to reach miniaturization and low power dissipation in a 2.4 GHz transceiver targeting wireless body area networks (WBAN) and wireless sensor networks (WSN) applications. Precise phase locking of the BAW digitally controlled oscillator (DCO) to the low- frequency temperature compensated oscillator is demonstrated. Additional cancellation within the ADPLL of the deterministic jitter induced by the bi-frequency mode on the 32 kHz clock is proven, with a residual modulation on the DCO command word corresponding to ±0.5 ppm relative frequency deviation. The RF resulting after frequency up-conversion of the system IF signal with the DCO shows an excellent phase noise of - 136.6 dBc/Hz at 1 MHz offset frequency, for a total synthesizer current consumption of 7.52 mA under 1.6 V supply. In addition, 1 Mb/s GFSK Bluetooth and Bluetooth Low Energy modulations have been successfully validated in transmission.

In this paper, analysis of a novel class of A/D converters based on asynchronous delta modulation (DM) is presented and a high level model is realized for the same. Using the high level model, analytical expressions are derived for the calculation of the inband signal-to-quantization noise ratio (SQNR) for the case of sinusoidal inputs and two-tone inputs. For the special case of sinusoidal inputs, an empirical formula is also derived for calculating the inband SQNR. The derived analytical and empirical expressions are verified using high level simulations and the simulation results are presented finally.

This paper presents for the first time a theoretical study of the second order effects of a 4-bit Phase-domain Analog-to-Digital Converter (ADC) circuit for QPSK demodulation and analyzes its benefits and drawbacks. The study encompasses the phase resolution, dynamic range and robustness of this circuit to circuit non-idealities and noise. Our analysis shows that the phase ADC is extremely robust against circuit non-linearities, offsets and noise while providing a large dynamic range compared to traditional amplitude ADCs.

A sub-sampling based multiband RF front end suitable for medical telemetry applications is presented. Using a single inductor and a single sampling frequency it is shown how to downconvert concurrently Bluetooth LE and MICS band signals to baseband with relative attenuation of 42 dB between the two downconverted bands. The proposed front end is analyzed in detail and the results are validated using Spectre RF simulations for a 0.18μm CMOS process.

The WiseNET system includes an ultra low-power system-on-chip (SoC) hardware platform and WiseMAC, a low power medium access control protocol (MAC) dedicated to duty-cycled radios. Both elements have been designed to meet the specific requirements of wireless sensor networks and are particularly well suited to ad-hoc and hybrid networks. The WiseNET radio offers dual-band operation (434-MHz and 868-MHz) and runs from a single 1.5-V battery. It consumes only 2.5-mW in receive mode with a sensitivity smaller than−108-dBm at a BER of 10−3 and for a 100-kb/s data rate. In addition to this low-power radio, the WiseNET system-on-chip (SoC) also includes all the functions required for data acquisition, processing and storage of the information provided by the sensors. Ultra-low power consumption with the WiseNET system is achieved thanks to the combination of the low power consumption of the transceiver and the high energy efficiency of the WiseMAC protocol. The WiseNET solution consumes more than 250 times less power than comparable solutions based on the IEEE 802.15.4 standard.

LSI2

Two realizations of a differential and a quadrature injection-locked frequency dividers are proposed. The topologies utilize the injection-locking mechanism of a bipolar-junction transistor (BJT) single-ended Colpitts oscillator where the locking signal is injected through the base terminal. By considering the phase relationship between the input and the output signals under the divide-by-2 locking condition, a differential and a quadrature versions can be implemented without significantly modifying the single-ended topology. The theory on the prediction of the maximum relative locking range of the three versions of the dividers favorably match the experimental results using discrete components

WiseMAC is a medium access control protocol designed for the WiseNET™ wireless sensor network. It is based on CSMA and uses the preamble sampling technique to minimize the power consumed when listening to an idle medium. A unique feature of this protocol is to exploit the knowledge of the sampling schedule of its direct neighbors in order to use a wake-up preamble of minimized size. This scheme allows not only to reduce the transmit and the receive power consumption, but also brings a drastic reduction of the energy wasted due to overhearing. Backoff and medium reservation schemes have been selected to provide fairness and collision avoidance. WiseMAC requires no set-up signaling, no network-wide time synchronization and is adaptive to the traffic load. It provides an ultra-low average power consumption in low traffic conditions and a high energy efficiency in high traffic conditions.

In all-wireless networks a crucial problem is to minimize energy consumption, as in most cases the nodes are battery-operated. We focus on the problem of power-optimal broadcast, for which it is well known that the broadcast nature of the radio transmission can be exploited to optimize energy consumption. Several authors have conjectured that the problem of power-optimal broadcast is NP-complete. We provide here a formal proof, both for the general case and for the geometric one; in the former case, the network topology is represented by a generic graph with arbitrary weights, whereas in the latter a Euclidean distance is considered. We then describe a new heuristic, Embedded Wireless Multicast Advantage. We show that it compares well with other proposals and we explain how it can be distributed.

A broad range of new high-volume consumer applications require the availability of low-power, battery operated, wireless microsystems. These systems should conciliate a sufficient battery lifetime with reduced overall dimensions (including antenna), low cost and versatility. The design of such systems highlights many tradeoffs between performances, cost and power consumption. These considerations led our group to choose a direct-conversion scheme for a distributed sensors application. The key blocks for this architecture have been realized and measured in a 0.5 /spl mu/m CMOS technology, validating this approach. From these results, the total power consumption of a receiver operating in the 433 MHz ISM band is expected as low as 1.4 mW, under 1.2 V supply, for a sensitivity of -100 dBm and a 20 kbit/s data rate. The transmitter provides 9 dBm output power under the same supply voltage, with a 35% efficiency.

A broad range of high-volume consumer applications require low-power, battery operated, wireless microsystems and sensors. These systems should reconcile a sufficient battery lifetime with reduced dimensions, low cost and versatility. The design of such systems highlights many tradeoffs between performances, lifetime, cost and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V). These considerations are illustrated by design examples taken from a transceiver chip realized in a standard 0.5 /spl mu/m digital CMOS process. The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture. The circuit prototype operates in the 434 MHz ISM band and consumes only 1 mW in receive mode. It achieves a -95 dBm sensitivity for a data rate of 24 kbit/s. The transmitter section is designed for 0 dBm output power under the minimum 1 V supply, with a global efficiency higher than 15%.

Autonomous transceivers working in the ISM' UHF hands should meet both requirements of a long battery lifetime and a small overall volume, thus implying to cut the receiving power consumption down to less than 1 mW.Ultimately, this goal will only be reached by using original topologies and lowering the supply voltage down to single battery cell operation.A RF front-end and a power-amplifier (PA) designed for the 433 MHz European ISM band are presented.Both RF building blocks have been integrated in a standard 0.5 urn digital CMOS process with 0.65 V threshold voltages.The front-end includes an LNA and a downconverter mixer.It achieves a total double sideband (DSB) noise figure of 9 dB, with a dynamic range of 8.5 dB for a 60 kHz bandwidth, while dissipating only 250 uW at 1.2 V supply voltage.The PA includes two fully integrated Class A stages together with an output Class C amplifier.It achieves a +4 dBm output power with a 15 % overall efficiency under 1.2 V supply voltage.

In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Recent availability of the public-domain EKV (Enz-Krummenacher-Vittoz) MOST model from EPFL in a number of circuit simulators facilitates the intuitive design, analysis and simulation of analogue and mixed-mode circuits and systems exploring the numerous modes of operation of the MOST, particularly at low-voltage (LV) and low-current (LC). A practical approach for either extracting the most critical parameters and/or adapting those already available from widely used SPICE models (levels 2 and 3) for use with the EKV model is presented and opportunities for engineering education are considered. The effectiveness of the approach is illustrated by measured results from CMOS and BiCMOS technologies.

This paper presents a new BiCMOS OTA based on MOS transistors operating in the triode-region. The THD of the proposed OTA is smaller than -63 dB for an input voltage up to 2 Vp-p at 3 V supply voltage. The Common-Mode (CM) stabilization systems, combining both CM Feed Forward and CM Feed Back circuits are also presented. Simulated results of a second-order filter designed using the proposed OTA are given.