Shang-Wei Tu

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2ranked-venue papers

2as first author

0since 2021 · last 2006

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Electronic design automation · 88% Integrated circuit design · 12%

Topics — the 4 heaviest of 4, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Electronic design automation › physical design interconnect optimization	0.1	1	2006	RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation physical design	0.1	1	2006	RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation › physical design › timing optimization delay optimization	0.0	1	2006	RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Integrated circuit design digital circuit design	0.0	1	2006	RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006

Methods — techniques the papers use, named apart from their topics

bus-invert encoding · 0.1RLC coupling-aware simulation · 0.1

Year	Publication	Venue	Position
2006	RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction abstract This paper shows that the worst case switching pattern that incurs the longest bus delay while considering the RLC effect is quite different from that while considering the RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. A bus-invert method is also proposed to reduce the on-chip bus delay based on the RLC model. Simulation results show that the proposed encoding scheme significantly reduces the worst case coupling delay of the inductance-dominated buses Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1
2004	Layout techniques for on-chip interconnect inductance reduction Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang	ASP-DAC	1