The paper proposes a combined approach of Solar and wind power fluctuation equalization through Electrochemical Ammonia Synthesis (EAS) and Direct Ammonia Fuel Cells (DAFCs), supplemented by different smoothing filters. When full of renewable energy, the surplus is turned into ammonia and stored and later turned back into electricity when there is a shortage. It uses Moving Average, Moving Median, Moving Regression, Gaussian and Savitzky Golay filters on real wind and solar profiles in MATLAB and uses EAS/DAFC models in Engineering Equation Solver (EES). Findings indicate that the MR filter provides the best compromise between noise attenuation and trend fidelity, and peak capacity demands of ammonia production and fuel cell output are lowered by approximately$\mathbf{1 0 - 2 0 \%}$relative to raw profiles. SG and Gaussian filters have nearly similar advantages, whereas MA and MM are suboptimal because of either lag or inconsistent trend. This is the novelty of the work because a comparative evaluation of advanced smoothing methods in an ammonia-based storage cycle has never been carried out, and results are used to inform actionable recommendations regarding storage cycle sizing and cost minimization. The suggested methodology increases the stability of the grid, reduces the sizing of subsystems, and enables the cost-efficient implementation of ammonia fuel cells to integrate renewable energies.

Phase Frequency Detectors (PFDs) are essential components in Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) systems, responsible for comparing phase and frequency differences and generating up/down signals to regulate charge pumps and/or, consequently, Voltage-Controlled Oscillators (VCOs). Conventional PFD designs often suffer from significant dead zones and blind zones, which degrade phase detection accuracy and increase jitter in high-speed applications. This paper addresses PFD design challenges and presents a novel low-power True Single-Phase Clock (TSPC)-based PFD. The proposed design eliminates the blind zone entirely while achieving a minimal dead zone of 40 ps. The proposed PFD, implemented using TSMC 28 nm technology, demonstrates a low-power consumption of $4.41 \mu W$ at $\mathbf{3 ~ G H z}$ input frequency with a layout area of $10.42 \mu \mathrm{~m}^{2}$.

While general-purpose computing follows von Neumann’s architecture, the data movement between memory and processor elements dictates the processor’s performance. The evolving compute-in-memory (CiM) paradigm tackles this issue by facilitating simultaneous processing and storage within static random-access memory (SRAM) elements. Numerous design decisions taken at different levels of hierarchy affect the figures of merit (FoMs) of SRAM, such as power, performance, area, and yield. The absence of a rapid assessment mechanism for the impact of changes at different hierarchy levels on global FoMs poses a challenge to accurately evaluating innovative SRAM designs. This article presents an automation tool designed to optimize the energy and latency of SRAM designs incorporating diverse implementation strategies for executing logic operations within the SRAM. The tool structure allows easy comparison across different array topologies and various design strategies to result in energy-efficient implementations. Our study involves a comprehensive comparison of over 6900+ distinct design implementation strategies for École Polytechnique Fédérale de Lausanne (EPFL) combinational benchmark circuits on the energy-recycling resonant CiM (rCiM) architecture designed using Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm technology. When provided with a combinational circuit, the tool aims to generate an energy-efficient implementation strategy tailored to the specified input memory and latency constraints. The tool reduces 80.9% of energy consumption on average across all benchmarks while using the six-topology implementation compared with the baseline implementation of single-macro topology by considering the parallel processing capability of rCiM cache size ranging from 4 to 192 kB.

In recent years, Compute-in-memory (CiM) architectures have emerged as a promising solution for deep neural network (NN) accelerators. Multiply-accumulate (MAC) is considered a de facto unit operation in NNs. By leveraging the minimal data movement required and inherent parallel processing capabilities of CiM, NNs that require numerous MAC operations can be executed more efficiently. Traditional CiM architectures execute MAC operations in the analog domain, employing an Analog-to-Digital converter (ADC) to digitize the analog MAC values. However, these ADCs introduce significant increase in area and power consumption, as well as introduce non-linearities. This work proposes a resonant time-domain CiM (rTD-CiM), an ADC-less architecture that reduces the power consumption of traditional CiM architectures with ADCs. The feasibility of the proposed architecture is evaluated on an 8KB SRAM memory array using TSMC 28 nm technology. The proposed rTD-CiM architecture demonstrates a throughput of 2.36 TOPS with an energy efficiency of 28.05 TOPS/W.

Traditional State-of-the-Art computing platforms have relied on silicon-based static random access memories (SRAM) and digital Boolean logic for intensive computations. Although the metal-oxide-semiconductor transistors have been aggressively scaled, the fundamental von-Neumann computing architecture has remained unaltered. The emerging paradigm of Compute-in-Memory (CIM) offers a promising solution to overcome the memory wall bottleneck in traditional von-Neumann architectures by enabling the processing and storing of information within SRAM memory elements. This article introduces an energy-recycling resonant 10T-SRAM architecture that facilitates in-memory computations to minimize the need for data movement between the processing core and memory. Series resonant write driver is utilized to efficiently recycle the discharged energy during a writing operation to reduce the overall energy consumption of the SRAM architecture. The feasibility of the proposed rCIM has been demonstrated by implementing it on an 8KB memory array using TSMC 28nm PDK. Additionally, a comprehensive Monte Carlo variation analysis was conducted to ensure the robustness and reliability of the scheme under process variations. To demonstrate the effectiveness of the proposed architecture, we evaluate its performance using the EPFL combinational benchmark suite. The proposed Resonant Compute-In-Memory (rCIM) consumes 55.42% lower energy than standard von-Neumann architecture and achieves a throughput of 88.2-106.6 GOPS/s.

As the demand for high-performance microprocessors increases, the circuit complexity and the rate of data transfer increases resulting in higher power consumption. We propose a clocking architecture that uses a series LC resonance and inductor matching technique to address this bottleneck. By employing pulsed resonance, the switching power dissipated is recycled back. The inductor matching technique aids in reducing the skew, increasing the robustness of the clock network. This new resonant architecture saves over 43% power and 91% skew clocking a range of 1-5 GHz, compared to a conventional primary-secondary flip-flop-based CMOS architecture.

The controller area network (CAN) is the most widely used intra-vehicular communication network in the automotive industry. Because of its simplicity in design, it lacks most of the requirements needed for a security-proven communication protocol. However, a safe and secured environment is imperative for autonomous as well as connected vehicles. Therefore CAN security is considered one of the important topics in the automotive research community. In this article, we propose a four-stage intrusion detection system that uses the chi-squared method and can detect any kind of strong and weak cyber attacks in a CAN. This work is the first-ever graph-based defense system proposed for the CAN. Our experimental results show that we have a very low 5.26% misclassification for denial of service (DoS) attack, 10% misclassification for fuzzy attack, 4.76% misclassification for replay attack, and no misclassification for spoofing attack. In addition, the proposed methodology exhibits up to 13.73% better accuracy compared to existing ID sequence-based methods.

At leading technology nodes, the industry is facing a stiff challenge to make profitable ICs. One of the primary issues is the design rule checking (DRC) violation. In this research, we cohort with the DARPA IDEA program that aims for "no-human-in-the-loop" and 24-hour turnaround time to implement an IC from design specifications. In order to reduce human effort, we introduce the ensemble random forest algorithm to predict DRC violations before global routing, which is considered the most time-consuming step in an IC design flow. In addition, we identified features that critically impact the DRC violations. The algorithm has a 5.8% better F1-score compared to the existing SVM classifiers.

In a high-performance VLSI design, the clock network consumes a significant amount of power. While most existing methodologies use voltage-mode (VM) signaling, these clock distributions lose a tremendous amount of dynamic power to charge/discharge the large global clock capacitance. New circuit approaches for current-mode (CM) clocking save significant clock power, but have been limited to only symmetric networks, while most application specific integrated circuits have asymmetric clock distributions. In this paper, we propose the first CM clock synthesis (CMCS) methodology to reduce the overall clock network power with low skew. The method can integrate with traditional clock routing followed by transmitter and receiver sizing. We validate the proposed methodology using ISPD 2009 and 2010 industrial benchmarks using an extracted SPICE model distributed in 1.4-275.6-mm2area and consists of 81-2249 sinks. This methodology saves 39%-84% average power with similar skew on the benchmarks using 45-nm CMOS technology simulation of clock frequencies range from 1-3 GHz. In addition, the CMCS methodology takes 2.4-9.1× less running time and consumes 20%-26% less transistor area compared with synthesized, buffered VM clock distributions.

Clock Distribution Networks (CDNs) in high speed designs can consume 30-50% of the total chip dynamic power. Adiabatic clock circuits can save some of this power, but these depend on a time varying power supply which is difficult to implement in practice. In this paper, we present the first quasi-adiabatic clock circuit with a constant supply voltage at high speeds. Our proposed adiabatic clocks attain an average 23% clock power savings with better slew rate and the same skew compared to traditional buffered clocks.

Distributed-LC resonant clock distribution is a viable technique to reduce clock distribution network (CDN) dynamic power. However, resonant clocks can require significant on-chip resources to form the inductors and decoupling capacitors which discourages adoption. This paper uses a compensation capacitor (Cc) to reduce the overhead of the on-chip inductor and capacitor resources without changing the performance of a distributed-LC resonant clock. Analysis on the ISPD clock benchmarks show nearly 12% reduction in passive device area compared to previous resonant clocks while still saving 49.9% power over traditional buffered clocks.

We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flip-flop (CMPFF) using a representative 45 nm CMOS technology. When the CMPFF is combined with a CM transmitter, the first CM clock distribution network exhibits 45.2% lower average power compared to traditional voltage mode clocks.