EDBT 2026 Demo / reviewers in the wild / expert
K. C. Ng
dblp:86/1193
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Computer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer networks
1 paper |
Internet architecture and protocols · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 87% Electronic design automation · 13% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Internet architecture and protocols
information-centric networking |
0.2 | 1 | 2013 | Less pain, most of the gain: incrementally deployable ICN · SIGCOMM 2013 |
Internet architecture and protocols › information-centric networking
in-network caching |
0.0 | 1 | 2013 | Less pain, most of the gain: incrementally deployable ICN · SIGCOMM 2013 |
Hardware accelerators and domain-specific architectures › scientific computing accelerator
circuit simulation acceleration |
0.0 | 1 | 1987 | A Vector Hardware Accelerator with Circuit Simulation Emphasis · DAC 1987 |
Hardware accelerators and domain-specific architectures › data-parallel accelerator
vector accelerator |
0.0 | 1 | 1987 | A Vector Hardware Accelerator with Circuit Simulation Emphasis · DAC 1987 |
Electronic design automation
circuit simulation |
0.0 | 1 | 1987 | A Vector Hardware Accelerator with Circuit Simulation Emphasis · DAC 1987 |
Methods — techniques the papers use, named apart from their topics
trace-driven simulation · 0.2pipelined floating-point processing · 0.0SIMD architecture · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2013 | Less pain, most of the gain: incrementally deployable ICNabstractInformation-Centric Networking (ICN) has seen a significant resurgence in recent years. ICN promises benefits to users and service providers along several dimensions (e.g., performance, security, and mobility). These benefits, however, come at a non-trivial cost as many ICN proposals envision adding significant complexity to the network by having routers serve as content caches and support nearest-replica routing. This paper is driven by the simple question of whether this additional complexity is justified and if we can achieve these benefits in an incrementally deployable fashion. To this end, we use trace-driven simulations to analyze the quantitative benefits attributed to ICN (e.g., lower latency and congestion). Somewhat surprisingly, we find that pervasive caching and nearest-replica routing are not fundamentally necessary---most of the performance benefits can be achieved with simpler caching architectures. We also discuss how the qualitative benefits of ICN (e.g., security, mobility) can be achieved without any changes to the network. Building on these insights, we present a proof-of-concept design of an incrementally deployable ICN architecture. Seyed Kaveh Fayaz, Yin Lin, Amin Tootoonchian, Ali Ghodsi 0002, Teemu Koponen, Bruce M. Maggs, K. C. Ng, Vyas Sekar, Scott Shenker |
SIGCOMM | 7 |
| 1987 | A Vector Hardware Accelerator with Circuit Simulation EmphasisabstractA floating-point vector accelerator has been built which runs circuit simulation efficiently. The design considerations of the accelerator are based on the time-consuming parts of SPICE2, available off-the-shelf parts, advanced software tools experience and cost/performance. The three board accelerator can run the entire application program complied from a high-level language. A personal workstation, such as the PC-AT, is used for the general I/O tasks such as file handling and network support. The processor has a Single-Instruction Multiple-Data 64-bit floating-point pipelined architecture. It can achieve a maximum speed of 8 Mips and 8 MFlops. A floating-point processor based on two functional units, a multiplier and an ALU, and an integer processor work in parallel to achieve the high performance. The accelerator attached to a PC-AT runs SPICE2 60 times faster than the personal workstation alone and achieves double the performance of a VAX 8650. Andrei Vladimirescu, Manolis Katevenis, Zvika Bronstein, Alon Kifir, Karja Danuwidjaja, K. C. Ng, Niraj Jain, Steven Lass |
DAC | 7 |