In this paper, we propose a fast template-based analog layout retargeting methodology, which can support general device abstraction and versatile device replacement. In order to achieve high efficiency, the original circuit devices are substituted by abstract devices during the retargeting process. The layout is then retargeted with the aid of a constraint graph, which can not only preserve the layout knowledge, but also tune the device placement by acute user-defined constraints. The retargeted abstract devices are finally replaced by parametrized cells (PCells) to generate the target layout. Our experimental results show that the abstract-device-inclusive retargeting process is much faster than the traditional layout retargeting scheme, and the proposed methodology is general to be applied to any basic analog building blocks and especially beneficial to the radio-frequency (RF) circuits.

As the technology node continuously scales down, layout-dependent effects (LDEs) have been significantly affecting the threshold voltage and mobility of MOSFET transistors and then, in turn, the performance of analog integrated circuits. In this paper, we propose an LDE optimization methodology based on the evolutionary algorithm, which aims to protect analog circuits from the LDE-induced circuit performance degradation. With the aid of a fast analog layout retargeting scheme, our proposed optimization can evaluate the circuit performance with the consideration of detailed physical layouts, tune the device placement and transistor finger number, and modify the layout patterns for the LDE-aware circuit performance preservation. To accelerate the physical layout synthesis, our new retargeting process supports general device abstraction. The experimental results show that our proposed methodology can more effectively preserve analog and even RF circuit performance with higher efficiency than the alternative approaches.

For analog integrated circuits (ICs) in nanometer technology nodes, process variation (PV) induced by lithography may not only cause serious wafer pattern distortion, but also result in device mismatch, which can readily ruin circuit performance. Although the conventional optical proximity correction (OPC) operations can effectively improve the wafer image fidelity, an analog circuit without robust device sizes is still highly vulnerable to such a mismatch effect. In this article, a PV-aware sizing-inclusive analog layout retargeting framework, which encloses an efficient hybrid OPC scheme for yield enhancement, is proposed. The device sizes are tuned during the layout retargeting process by using a deterministic circuit-sizing algorithm considering PV conditions. Our hybrid OPC method combines global rule-based OPC with local model-based OPC functions to boost the wafer image quality improvement but without degrading the computational efficiency. The experimental results show that our proposed framework can achieve the best wafer image quality and circuit performance preservation compared to any other alternative approaches.

For high-quality analog layout retargeting, in this brief we propose a hybrid optical proximity correction (OPC) methodology, which features special handling against geometry manufacturing deviation caused by process variation (PV). Based on the unique nature of analog layouts, accuracy limitation of the rule-based OPC (RB-OPC) is compensated by geometry preprocessing operations in our proposed layout retargeting flow, and is further shrunk by a local model-based OPC postprocessing operation without incurring any chip area increment. An innovative RB PV-band correction scheme is developed to preserve analog circuit performance against possible PV. The experiments show that our analog layout retargeting flow integrated with the proposed PV-aware hybrid OPC can achieve much higher efficiency with even lower mask complexity and edge placement error compared to alternative methods.

In this paper, we propose a rule-based OPC (RB-OPC) algorithm considering process variation (PV) and integrate it into an analog layout retargeting platform. We apply interconnect wire operations during the retargeting process to compensate the accuracy limitation of the RB-OPC method. A PV-band shifting scheme is used to handle PV-induced-mismatch on circuit matching blocks. From our experimental results, it is observed that the proposed RB-OPC method can achieve acceptable wafer image fidelity compared to other time-consuming alternative solutions yet with much less mask complexity. And the mismatch effect is greatly alleviated by our PV-band handling scheme in different PV corners.

Optical proximity correction (OPC) is invaluable to precise layout manufacturing in the advanced nanometer technologies. However, lack of research activity on OPC for analog integrated circuits has currently led to sole dependence on digital solutions. In this paper, we propose a rule-based OPC (RB-OPC) methodology with process variation (PV) consideration, which is integrated into an analog layout migration process. Based on the unique features of analog layouts, the accuracy limitation of RB-OPC is compensated by local wire widening and wire shifting operations during layout migration. Moreover, innovative PV-band shifting is deployed to preserve analog circuit performance against PV. According to our experimental results, the proposed analog layout migration with PV-aware RB-OPC can achieve much higher efficiency with an even lower mask complexity and an acceptable edge placement error compared to some well-known commercial and academic digital solutions. The circuit performance by using our proposed methodology is also better than that from alternative methods in the mismatch scenarios due to our special PV-band handling on transistor gates.

In this paper a yield-aware template-based analog layout retargeting methodology for lithography-friendly nanometer technology designs is proposed. The yield performance is evaluated by probability of failure (POF), which is independent of any specific defect size, and is improved by wire-widening and wire-shifting inside the retargeting process. The non-traditional design rules, which are becoming prominent in the advanced nanometer technologies, have been tackled in the template. The retargeting flow is demonstrated from 0.18um CMOS technology to 65nm CMOS technology with significant yield improvement.

Photolithographic defects during manufacture cannot only result in significant yield loss in digital integrated circuits, but are also deemed as an important factor in evaluating the quality of analog layouts. In this paper, we propose a graph-based lithography-aware analog layout retargeting methodology. We build up our fault model based on a classical defect size distribution function, geometrical critical area analysis, and probability of failure (POF). The objective of our algorithm is to minimize POF by intelligent redundant space allocation scheme during layout compaction. The optimizations handle the whole analog layout area by global wire widening, intradevice wire shifting (WS), and interdevice WS, which are achieved by updating the constraint-graph representation of the layout. Moreover, we propose an extra space allocation approach that can further reduce POF by an inconsiderably small chip-area compromise. The yield improvement and superior effectiveness of our algorithm are exhibited by retargeting operational amplifiers and being compared with a traditional linear programming-based layout compaction method and a well-known even wire distribution scheme.

Lithographic effects have long been a primary yield consideration during integrated circuit (IC) manufacture. Especially the random spot defects may easily lead to functional failures across the chip. In this paper, a lithography-friendly analog layout migration flow is proposed. The optimization is achieved by intelligent redundant space utilization, which includes wire widening and wire shifting in order to minimize global probability of failure. We also propose a way of effectively reduce the probability of failure by a reasonable chip area compromise. Our experimental results indicate significant yield improvement for both short and open type faults.