Traditionally, it had been assumed that the efficiency requirements of TCP dictate that the buffer size at the router must be of the order of the bandwidth-delay (C× RTT) product. Recently, this assumption was questioned in a number of papers, and the rule was shown to be conservative for certain traffic models. In particular, by appealing to statistical multiplexing, it was shown that on a router withNlong-lived connections, buffers of sizeO([(C× RTT)/(√N)]) or evenO(1) are sufficient. In this paper, we reexamine the buffer-size requirements of core routers when flows arrive and depart. Our conclusion is as follows: If the core-to-access-speed ratio is large, thenO(1) buffers are sufficient at the core routers; otherwise, larger buffer sizes do improve the flow-level performance of the users. From a modeling point of view, our analysis offers two new insights. First, it may not be appropriate to derive buffer-sizing rules by studying a network with a fixed number of users. In fact, depending upon the core-to-access-speed ratio, the buffer size itself may affect the number of flows in the system, so these two parameters (buffer size and number of flows in the system) should not be treated as independent quantities. Second, in the regime where the core-to-access-speed ratio is large, we note that theO(1) buffer sizes are sufficient for good performance and that no loss of utilization results, as previously believed.

Traditionally, it had been assumed that the efficiency requirements of TCP dictate that the buffer size at the router must be of the order of the bandwidth (C)-delay (RTT) product. Recently this assumption was questioned in a number of papers and the rule was shown to be conservative for certain traffic models. In particular, by appealing to statistical multiplexing it was shown that on a router with N long-lived connections, buffers of size O(CxRTT)/radic(N) or even O(1) are sufficient. In this paper, we reexamine the buffer size requirements of core routers when flows arrive and depart. Our conclusion is as follows: if the core to access speed ratio is large, then O(1) buffers are sufficient at the core routers; otherwise, larger buffer sizes do improve the flow-level performance of the users. From a modeling point of view, our analysis offers two new insights. First, it may not be appropriate to derive buffer-sizing rules by studying a network with a fixed number of users. In fact, depending upon the core-to-access speed ratio, the buffer size itself may affect the number of flows in the system, so these two parameters (buffer size and number of flows in the system) should not be treated as independent quantities. Second, in the regime where the core-to- access speed ratio is large, we note that the O(1) buffer sizes are sufficient for good performance and that no loss of utilization results, as previously believed.

In this paper, we evaluate the performance of both real and virtual queue-based marking schemes designed for use at routers in the Internet. Using fluid flow models, we show via analysis and simulations that Virtual Queue (VQ)-based marking schemes outperform Real Queue (RQ)-based marking schemes in terms of robustness to disturbances and the ability to maintain low queueing delays. In fact, we prove that a linearized model of RQ-based marking schemes exhibit a lack of robustness to constant but otherwise unknown levels of disturbances. The analytical results we present are applicable to combinations of proportionally fair and TCP-type congestion controllers at the source, and Random Exponential Marking (REM) and Proportional Control (PC) schemes at the router. The behavior of Random Early Discard (RED) and Proportional-Integral (PI) control schemes at the router are also studied via simulations.

A methodology is presented for constructing models of manufacturing processes for simulation and design of the discrete control logic. The models represent the discrete event evolution of the system as well as features of the underlying continuous processes. For applications such as discrete parts manufacture and assembly, the process is decomposed into operations with specified precedence relations. For each operation the required resources and associated discrete resource states are identified. Also associated with each resource is a set of resource attributes which are modified by the processes underlying each operation. The structure of the discrete-level control is modeled by modified Petri nets which are synthesized from single resource activity cycles. Construction of the net provides discrete control logic for error recovery loops and other real-time decision structures with guaranteed properties based on extensions of previous results in Petri net theory. The modeling methodology is applied to a two-arm robotic assembly cell example.