In this paper we introduce a new method of performing direct solution of the harmonic balance Jacobian. For examples with moderate number of harmonics and moderate to strong nonlinearities, we demonstrate that the direct solver has far superior performance with a moderate increase in memory compared to the best preconditioned iterative solvers. This solver is especially suited for Fourier envelope analysis where the number of harmonics is small, circuits are nonlinear and Jacobian bypass can be used for additional speed. For examples with large number of harmonics and moderate to strong nonlinearities, the performance advantage is maintained but the memory requirements increase. We propose efficient preconditioners based on direct solution of harmonic balance matrices which provide the user with a memory-speed trade-off.

This paper presents a generalized formulation of the periodic steady-state analysis for oscillators. The new formulation finds the value of a circuit parameter that results in a desired oscillation frequency for the circuit. Numerical methods based on the time-domain finite difference and shooting methods, and the frequency-domain harmonic balance method are described. Comparisons with search-based methods demonstrate the efficacy of the new approach.

In this paper a modification of the time-domain periodic steady-state analysis for oscillators is presented. The proposed analysis finds the value of a circuit parameter that results in the circuit oscillating at a desired frequency. This analysis is based on the steady-state analysis for voltage and current controlled oscillators, i.e., replacing the oscillation period by a circuit parameter in the list of unknowns. A generalized formulation that can handle a control voltage or current, as well as any frequency-tuning circuit parameter, such as a tank capacitor or device geometry is developed in this paper.

This paper introduces the problem of finding the steady-state and the numerical value of the controlling voltage or current for oscillators where the frequency of oscillation is known beforehand. These situations are very common when the oscillator is part of a phase-locked loop (PLL). In PLLs, the reference frequency as well as the divide ratios are known at the time of design. Therefore the desired frequency of the voltage (current) controlled oscillator is known but not the controlling voltage (current). We formulate this problem as the solution of an appropriate nonlinear equation. We present robust and efficient numerical techniques for solving this nonlinear equation both in time and frequency domain. We demonstrate using experimental results that this technique is at par with classical methods of calculating oscillator steady-state and period of oscillation for a given control voltage. We show that compared to a search-based approach to calculating the desired control voltage or current, our direct method is a order of magnitude faster for the same accuracy.

In this paper, we present a methodology for systematically optimizing the power-supply voltage for either maximizing the performance of very large scale integration (VLSI) circuits or minimizing the power dissipation in technologies where leakage power is not an insignificant fraction of the total power dissipation. For this purpose, we develop simplified empirical equations that describe the transistor behavior as a function of power supply and temperature. We use these models to calculate the full-chip power dissipation as a function of power supply and temperature. We then solve the power and chip thermal equations simultaneously to calculate the chip temperature and power dissipation at a given power supply. By varying the power-supply voltage, we determine the optimum V/sub DD/ value that minimized delay per unit length in global interconnects and therefore maximizes performance. Using the same framework, by again varying the supply we find the optimum V/sub DD/ that minimized the total power dissipation while maintaining a given delay per unit length. We show that for 90- and 65-nm technologies, where leakage power represents a significant fraction of the total power dissipation, optimum V/sub DD/ for maximum performance is lower than the International Technology Roadmap for Semiconductors (ITRS) specified supply voltage. This is due to the fact that reducing V/sub DD/ results in a large reduction in total power dissipation, and therefore the chip temperature, which improves performance. This improvement in performance is greater than the performance penalty incurred due to reduction in V/sub DD/. We also show that as the required delay per unit length is increased, total chip power consumption is reduced significantly if the power supply is also reduced as compared to the case when power supply is fixed at the nominal value. This change becomes larger with technology scaling due to the fact that leakage power, which is a very strong function of chip temperature, becomes a larger fraction of the full-chip power dissipation.

Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) based simultaneous optimization of supply (Vdd) and threshold (Vth) voltages. We present for the first time, the implications of an electrothermally aware EDP optimization on circuit operation in leakage dominant nanometer scale CMOS technologies. It is demonstrated that electrothermal EDP (EEDP) optimization restricts the operation of the circuit to a certain region in the Vdd-Vth plane. Also, the significance of EEDP optimization has been shown to increase with increase in leakage power and/or process variations.

This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Using these, a new and computationally efficient performance optimization techniques for distributed RLC interconnects has been introduced. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behavior and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in driver output resistance and input capacitance with scaling can make deep submicron designs increasingly susceptible to inductance effects if global interconnects are not scaled. For scaled global interconnects with increasing line resistance per unit length, as prescribed by the International Technology Roadmap for Semiconductors, the effect of inductance on interconnect performance actually diminishes.

This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behaviour and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in the driver capacitance and output resistance with scaling makes deep submicron (DSM) designs increasingly susceptible to inductance effects. Also, the impact of inductance variations on performance has been quantified. Additionally, the impact of the wire inductance on catastrophic logic failures and IC reliability issues have been analyzed.

Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the 130 nm technology node, performance improvement of advanced VLSI is likely to begin to saturate unless a paradigm shift from present IC architecture is introduced. This paper presents a comprehensive analytical treatment of ICs with multiple Si layers (3-D ICs). It is shown that significant improvement in performance (more than 145%) and reduction in wire-limited chip area can be achieved with 3-D ICs with vertical inter-layer interconnects (VILICs). This analysis is based on dividing a chip into separate blocks, each occupying a separate physical level. A scheme to optimize interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis. Furthermore, thermal analysis of ICs with two Si layers is presented. It is demonstrated that using a thermally responsible design and/or a high-performance heat sinking technology, die temperatures for ICs with two Si layers can be reduced well below present die temperatures. Finally, implications of 3-D architecture on several circuit designs are also discussed.

This work addresses the problem of noise analysis of phase locked loops (PLLs). The problem is formulated as a stochastic differential equation and is solved in presence of circuit white noise sources yielding the spectrum of the PLL output. Specifically, the effect of loop filter characteristics, phase-frequency detector and phase noise of the open loop voltage controlled oscillator (VCO) on the PLL output spectrum is quantified. These results are derived using a full nonlinear analysis of the VCO in the feedback loop and cannot be predicted using traditional linear analyses or the phase noise analysis of open loop oscillators. The computed spectrum matches well with measured results, specifically, the shape of the output spectrum matches very well with measured PLL output spectra reported in the literature for different kinds of loop filters and phase detectors. The PLL output spectrum computation only requires the phase noise of the VCO, loop filter and phase detector noise, phase detector gain and loop filter transfer function and does not require the transient simulation of the entire PLL which can be very expensive. The noise analysis technique is illustrated with some examples.

Article Free Access Share on On thermal effects in deep sub-micron VLSI interconnects Authors: Kaustav Banerjee Integrated Systems, Department of Electrical Engineering, Stanford University, Stanford, CA and Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA Integrated Systems, Department of Electrical Engineering, Stanford University, Stanford, CA and Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CAView Profile , Amit Mehrotra Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CAView Profile , Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CAView Profile , Chenming Hu Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CAView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999Pages 885–891https://doi.org/10.1145/309847.310093Published:01 June 1999Publication History 60citation1,225DownloadsMetricsTotal Citations60Total Downloads1,225Last 12 Months111Last 6 weeks22 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Publisher SiteeReaderPDF

We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout “fabric ” scheme eliminates the conventional no-tion of power and ground routing on the integrated circuit die. In-stead, power and ground are essentially “pre-routed ” all over the die. By a clever arrangement of power/ground and signal pins, we almost completely eliminate the capacitive effects between signal wires. Ad-ditionally, we get a power and ground distribution network with a very low resistance at any point on the die. Another advantage of our scheme is that the arrangement of conductors ensures that on-chip inductances are uniformly negligible. Finally, characterization of the circuit delays, capacitances and resistances becomes extremely simple in our scheme, and needs to be done only once for a design. We show how the uniform parasitics of our fabric give rise to a reliable and predictable design. We have implemented our scheme using public domain layout software. Preliminary results show that it holds much promise as the layout methodology of choice in DSM integrated circuit design. 1

Considers the important problem of noise analysis of non-autonomous nonlinear RF circuits in the presence of input signal phase noise. We formulate this problem as a stochastic differential equation and solve it in the presence of circuit white-noise sources. We show that the output noise of a nonlinear non-autonomous circuit, driven by a periodic input signal with phase noise, is stationary-not cyclostationary (as would be predicted by traditional analyses). We also show that effect of the input signal phase noise is to act as additional white noise source. This result is derived using a full nonlinear analysis of the problem and cannot be predicted by traditional linear analysis-based techniques. Input signal phase noise can be an important portion of the overall output noise of the non-autonomous circuit. In our opinion, existing analyses have not considered this effect in a rigorous manner. We also relate this solution to results of the existing nonlinear time-domain and frequency-domain methods of noise analysis and point out the modifications required for the present techniques. We illustrate our technique using an example.

Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact, nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterisation of timing jitter and spectral dispersion, for computing which we develop efficient numerical methods. We demonstrate our techniques on practical electrical oscillators, and obtain good matches with measurements even at frequencies close to the carrier, where previous techniques break down.

We propose an algorithm for area optimisation of sequential circuits through redundancy removal. The algorithm finds compatible redundancies by implying values over nets in the circuit. The potentially exponential cost of state space traversal is avoided and the redundancies found can all be removed at once. The optimised circuit is a safe delayed replacement of the original circuit. The algorithm computes a set of compatible sequential redundancies and simplifies the circuit by propagating them through the circuit. We demonstrate the efficacy of the algorithm even for large circuits through experimental results on benchmark circuits.

The SPEC benchmark system has traditionally been used for evaluating computer architectures. However, this system is too general and does not accurately reflect the performance of architectures on domain-specific applications. Moreover the CPU95 benchmark suite used in the SPEC system is compute-intensive, while many important domains of applications have memory intensive algorithms. In this work, we present a benchmarking methodology for such an application domain-CAD for VLSI design. We have created a benchmark suite consisting of CAD applications from each stage in a typical VLSI design flow. To exercise the memory organization, each application is run on a sequence of input designs of increasing size. We observed that increasing the input size causes non-monotonic variations in the performance of different machines. We simulate the caches of the benchmarked architectures to assess the effect of memory organization on performance.

This paper discusses characteristics of the ART2 (adaptive resonance theory) information processing model which emerge when applied to the problem of interpreting dynamic sensor data. Fast learn ART2 is employed in a supervised learning framework to classify process "fingerprints" generated from multi-sensor trend patterns. Interest in ART2 was motivated by the ability to provide closed classification regions, uniform hyperspherical clusters, feature extraction, and on-line adaption. Sensor data interpretation is briefly discussed with an emphasis on the unique attributes of the problem and the interaction with ART2 information processing principles. Pattern representations, e.g., time domain, which encode information in both magnitude and direction of the input vector are shown to be fundamentally incompatible with ART2. Complement coding is shown to solve this problem when the feature extraction capability of the ART2 network is disabled. Complement coding is also shown to preserve the clustering characteristics of the process "fingerprints" which are otherwise lost using the ART2 directional similarity measure. These issues are illustrated using an ART2-based monitoring system for a dynamically simulated chemical process.