Analog-to-digital converters (ADCs) are essential components in modern signal processing systems, but their performance is often constrained by non-idealities such as mismatches, gain errors, offsets, etc. Two most popular ADC toplogies, viz., Successive Approximation Register (SAR) ADC whose performance is mostly affected by capacitor mismatch and Pipelined ADCs whose performance is mostly affected by capacitor mismatch and gain errors are discussed in this paper. Machine learning (ML)-based calibration techniques have recently emerged as effective tools to mitigate these challenges and enhance ADC performance. This paper provides a comprehensive overview of ML-driven approaches for calibrating SAR and Pipelined ADCs, emphasizing key methodologies, advantages, and limitations. Additionally, traditional Least Mean Squares (LMS)-based calibration methods are discussed and shown to be a limiting case of ML-based calibration.

In an era, where the exponential growth of image data driven by the Internet of Things (IoT) is outpacing traditional storage solutions, this work explores and advances the potential of implicit neural representation (INR) as a transformative approach to image compression. INR leverages the function approximation capabilities of neural networks to represent various types of data. While previous research has employed INR to achieve compression by training small networks to reconstruct large images, no work has explored past the fundamental barrier of using one network per image. This work proposes a novel advancement by breaking this barrier and representing multiple images with a single network. By modifying the loss function during training, the proposed approach allows a small number of weights to represent a large number of images, even those significantly different from each other. A thorough analytical study of the convergence of this new training method is also carried out, establishing upper bounds that not only confirm the method’s validity but also offer insights into optimal hyperparameter design. The proposed method is evaluated on the Kodak, ImageNet, and CIFAR-10 datasets. Experimental results demonstrate that all 24 images in the Kodak dataset can be represented by linear combinations of two sets of weights, achieving a peak signal-to-noise ratio (PSNR) of 26.5 dB with as low as 0.2 bits per pixel (BPP). The proposed method matches the rate-distortion performance of state-of-the-art image codecs, such as BPG, on the CIFAR-10 dataset. Additionally, the proposed method maintains the fundamental properties of INR, such as arbitrary resolution reconstruction of images.

This paper presents an energy-efficient full-duplex simultaneous bidirectional (FD-SBD) signaling transceiver to double the aggregate data transfer per pin for serial links. For achieving FD-SBD signaling, the transceiver employs a resistor-transconductance (R-Gm) hybrid-based subtractor to enable concurrent transmission and reception of non-return to zero (NRZ) data stream on a single differential channel. The transmitter of a conventional current-mode R-Gm hybrid transmits through a split termination, which effectively reduces the impedance at the transmitting node and increases the power consumed by the transmitter by almost two times compared to the conventional current-mode logic (CML) transmitter. In this work, we have proposed a current-sharing topology by reusing the same transmitter current in both transceivers so that the power consumed by the transmitters is reduced by$2\times $. A prototype of the proposed transceiver has been implemented in 65 nm CMOS technology for full-duplex signaling across a short FR4 link with a 2.5 dB insertion loss at Nyquist frequency. Measured results give an energy efficiency of 1.7 pJ/b at an aggregate data rate of 8.6 Gb/s with a bit error rate (BER)$\lt 10^{-12}$.

This paper presents a prototype 9-bit 10MS/s cyclic Analog-to-Digital Converter (ADC) with reference scaling technique. The idea of reference scaling in cyclic ADC has yet to be explored, even though it has been used in pipelined ADC. The proposed ADC has two sub-ADC blocks along with two MDAC sampling networks and an OTA, which is shared between the two MDAC sampling networks in every alternative clock period. During the first bit-cycling phase, voltage swing is reduced, and reference voltages are scaled down by the same factor for the subsequent bit-cycling phases. A proof-of-concept ADC is designed and simulated in 65nm CMOS technology. This ADC achieves an SNDR of 52.5 dB and SFDR of 57.1 dB with a 1.2V peak-to-peak sinusoidal input signal of frequency 5MHz sampled at 10MHz while consuming$260\mu \mathrm{W}$power from 1.2V supply.

Spiking Neural Networks (SNNs) are closely related to the dynamics of the human brain and use spatiotemporal encoding of information to generate spikes. Implementing various neuronal models in hardware is a popular field of research aiming to mimic biological behavior. The leaky integrate-and-fire model of the neuron is generally chosen for hardware implementation owing to its simplicity and accuracy in modeling the neuron. This paper proposes an infinite impulse response (IIR) filter-based neuron model and describes a backpropagation-based training algorithm for an SNN built using the proposed neurons. The trained network is implemented on an Ultra96-V2 FPGA to validate the design and demonstrate the power and resource efficiency. The implemented design achieves an accuracy of 98.91% on the MNIST dataset and classifies images at 13,021 frames-per-second (FPS) with a 200 MHz clock while consuming$\approx 7.5\times$higher resource efficiency than previous publications.

This paper presents a dual voltage controlled oscillator (VCO) based integer-N phase locked loop (PLL) for navigation receiver operating at L 5-band and S-band. The PLL incorporates a multiplexer based extended range multi modulus divider (MMD) in the feedback path to cater to both L 5 and S band. Fabricated in UMC 65-nm CMOS, the PLL consumes 7.9 mW power from 1.0 V supply. The PLL achieves a phase-noise (PN) of −121 dBc/Hz and −120 dBc/Hz at 1 MHz offset for L 5 band and S-band, respectively achieving a best figure-of-merit (FoM) of 179.9 dBc/Hz.

This paper proposes time-domain modeling of Switched-Capacitor Converters (SCCs) with periodic inputs by homogenizing the state-space model which results in a closed form expression of the output voltage as a function of time. The method relies on fourier decomposition of the input signal thereby recasting the state-space model in homogeneous form to obtain the time-domain response of the system. Circuit level simulations for Ladder switched-capacitor converter topology shows excellent agreement with the time-domain behavior obtained using the proposed technique. The proposed technique gives more than three orders-of-magnitude improvement in simulation time and is not only restricted to SCCs but equally applicable to other networks that can be defined using state-space method.

This article proposes a low-power reconfigurable multimode low-noise amplifier (LNA) that can be configured for multiple narrowband as well as wideband operations while providing simultaneous input matching and output load reconfigurabilty. A component sharing technique and a component-Q-aware impedance-matching technique are introduced in the proposed LNA circuit. The proposed LNA, implemented in a United Microelectronics Corporation (UMC) 0.18-μm CMOS process, can operate in a narrowband mode with center frequencies around 1.8, 2.1, and 2.4 GHz as well as in a wideband mode (2-5 GHz). Measured results show that the LNA has achieved 14.1, 14.5, and 14.1 dB of voltage gain, 8.5, 8.2, and 8.7 dB of noise figure (NF) in 1.8-, 2.1-, and 2.4-GHz modes, respectively. In the wideband mode, the measured gain and the NF are 14.5 and 7.8 dB, respectively. The LNA consumes 2 and 3.8 mW of power from the 1.8-V supply in the narrowband and wideband modes, respectively.

This paper proposes a dc-to-1-GHz continuously tunable bandpass (BP) analog-to-digital converter (ADC). The tunability is realized by modifying the pipelined ADC-based fS/4 BP-ADC. A passive switched capacitor-based error-delaying circuitry is used to delay the quantization noise generated by a pipelined ADC by programmable number of cycles to realize various noise transfer functions and a continuum of notches that cover dc to 1 GHz. A prototype was designed and simulated in Global Foundry 55-nm LP CMOS process. It achieves signalto-noise ratio in excess of 80 dB in 15.625-MHz bandwidth while sampling at 500 MHz. The proposed architecture uses subsampling and aliasing to quantize signals from 54 to 890 MHz, which covers the over-the-air broadcast channels for North American Television system.

A switched capacitor low-side current sensing signal conditioning circuit with high dynamic range is demonstrated in AMS 0.35 μm, 3.3 V CMOS process. The design incorporates a Switched Capacitor Programmable Gain Amplifier (SC-PGA) and multi-bit second order ΔΣ-ADC. The switched capacitor eliminates the need for explicit level-shifting and chopping circuits thus facilitating sensing of input signal with zero common-mode. Both PGA and ΔΣ-ADC operate at 2 MHz sampling rate. The signal bandwidth (BW) for the design is 1 KHz with an Over Sampling Ratio(OSR) of 1024. The ΔΣ-ADC when tested stand-alone achieves an SNDR of 84 dB over a signal band of 1 kHz while consuming 2.14 mW of power thus achieving a Schreir's FoM of 163 dB. The complete signal-chain that includes the SC-PGA and ΔΣ-ADC achieves an SNDR of 73 dB while consuming 4.78 mW of power thus realizing a low-power and very sensitive low-side current sensing circuit that can sense currents from 1500 A down to 1 A across a 100 μΩ shunt resistor resulting in a voltage sensitivity of 100 μV and step-size of 36 μV.

High resolution pipelined Analog-to-Digital Converters (ADCs) exceeding 10-bits are thermal noise limited. Typically for low-power switched capacitor (SC) circuits, the thermal noise of the op amp is the dominant source of noise as compared to the switches. This paper proposes a thermal noise canceling technique for pipelined stages that cancels the thermal noise of the op amp. The technique involves capturing the noise by an auxiliary DAC and then canceling the noise in the signal path. Circuit level simulations are done in IBM 32 nm SOI process. A case study of thermal noise cancellation for various resolution pipelined ADCs is also done.

In pipelined analog-to-digital converters (ADCs), the spurious free dynamic range (SFDR) and signal-to-noise ratio depend strongly on the precision with which the interstage gain and capacitor mismatch terms are estimated using digital calibration techniques. This paper introduces a dithering-based calibration technique, which facilitates accurate estimation of the interstage gain and capacitor mismatch term with minimal hardware overhead, thus realizing pipelined ADCs that achieve the theoretical maximum SFDR. The proposed technique is validated both at system level using MATLAB and then at circuit level. A prototype 12-bit pipelined ADC operating at 500 MHz was designed in 55-nm global foundry LP-CMOS process. The prototype 12-bit ADC realized with op amp that have open-loop gains as low as 54 dB, but linearity ≈100 dB achieves an SFDR of 100.13 dB when calibrated using the proposed technique.

The complex valued matched filter correlators consume maximum power in the DS/SS CDMA receivers. These correlators accumulate 1024 samples lying in the range -7 to +7. This accumulation needs 3 data bits, 1 sign bit and 10 extra bits for overflow. Hence, the correlator can be implemented as a cascade of 4-bit full adder and a 10-bit incrementer. As a ripple carry adder (RCA) consumes the least power among all the existing adder architectures, we have implemented the 4-bit adder as a RCA. Previous incrementers were implemented as ripple counters. In this paper we propose a novel incrementer which is faster than a ripple counter based incrementer. Hence, it can be operated at a reduced voltage resulting in considerable power reduction. The incrementer is implemented using multiplexers, AND gates and TSPC registers. The ripple-counter correlator and the proposed incrementer correlator were laid out in MAGIC using 0.5µ CMOS technology followed by power estimation using HSPICE. It is shown that the proposed architecture requires 50% less power than a ripple counter based design.