We designed two compact in situ NBTI and oxide degradation sensors with digital outputs in 130 nm CMOS. The 308 μm2NBTI sensor and the 150 μm2oxide degradation sensor provide digital frequency outputs and are compatible with a cell-based design methodology without requiring analog supplies. The sensors enable high-volume data collection and monitoring of degradation mechanisms to guide dynamic control schemes and warn of impending device failure. Large scale data-collection permits improved modeling and the potential for insight into the underlying reliability mechanisms. The oxide degradation sensor monitors the change in gate leakage under stress conditions and is the first proposed of its kind. The NBTI sensor is 110× smaller than previous work and is designed to compensate for temperature variations during measurement. A maximum error of 2.2% is observed for the NBTI sensor under process, voltage, and temperature variations. It provides ΔVthmeasurement with 3σ accuracy of 1.23 mV from 40° C-110° C.

Reliability failure mechanisms, such as time-dependent dielectric breakdown (TDDB), electromigration, and negative bias temperature instability (NBTI), have become a key concern in integrated circuit (IC) design. The traditional approach to reliability qualification assumes that the system will operate at maximum performance continuously under worst case voltage and temperature conditions. In reality, due to widely varying environmental conditions and an increased use of dynamic control techniques, such as dynamic voltage scaling and sleep modes, the typical system spends a very small fraction of its operational time at maximum voltage and temperature. In this paper, we show how this results in a reliability ";slack"; that can be leveraged to provide increased performance during periods of peak processing demand. We develop a novel, real time reliability model based on workload driven conditions. Based on this model, we then propose a new dynamic reliability management (DRM) scheme that results in 20%-35 % performance improvement during periods of peak computational demand while ensuring the required reliability lifetime.

Reliability failure mechanisms, such as time dependent dielectric breakdown, electromigration, and thermal cycling have become a key concern in processor design. The traditional approach to reliability qualification assumes that the processor will operate at maximum performance continuously under worst case voltage and temperature conditions. However, the typical processor spends a very small fraction of its operational time at maximum voltage and temperature. In this paper, we show how this results in a reliability "slack" that can be leveraged to provide increased performance during periods of peak processor demand. We develop a novel, real time reliability model based on workload driven conditions. We then propose a new dynamic reliability management (DRM) scheme that results in 20-35% performance improvement during periods of peak computational demand while ensuring the required reliability lifetime.