Compute-in-memory-based accelerators have gained significant attention due to their promising potential. However, many studies in this area often focus solely on the accelerator's performance without considering the latency and energy consumption associated with external data access. Moreover, many have observed a gap in energy efficiency between the macro and the accelerator levels. Our work addresses this problem by proposing an SRAM CIM-based AI accelerator design that reduces additional memory access and mitigates the overhead associated with external data access. Our results demonstrate that lowering the ratio of total local memory capacity to total CIM macro capacity closes the energy efficiency gap between the macro level and the accelerator level.

This paper presents a charge redistribution based computing-in-memory (CIM) accelerator for convolutional neural networks (CNNs). This CIM macro adopts 9T static random access memory (SRAM) with a read-decoupled port to avoid read-disturbing and perform the analog computation for further diminishing the energy consumption per arithmetic operation. Weighted capacitor switching technique is proposed to achieve a better linearity performance than conventional current charging/discharging scheme and reduce the number of analog-to-digital converters (ADC). Moreover, low multiply-accumulate (MAC) value skipping technique is also proposed to enhance the speed and reduce the power consumption of the CIM macro by skipping the first few bits during the analog-to-digital conversion. The proposed CIM macro was fabricated in TSMC 40-nm CMOS process. Measurement results show that the proof-of-concept prototype achieves an energy efficiency of 12.02 TOPS/W under 8-bit input and 8-bit weight resolution.

This paper presents a physical unclonable function (PUF) embedded in a 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC). There are two operation modes in this design: PUF mode and ADC mode. In the PUF mode, this design realizes the physically unclonable function by manipulating the capacitor array in the SAR ADC. Only a little area overhead is required for implementing the PUF. An offset cancellation circuit is employed to improve the uniformity of the PUF design. The proposed PUF is authenticated using Challenge Response Pairs (CRPs). Reliability and Uniqueness of the CRPs are 97.69% and 48.01%, respectively. Uniformity of the CRPs is 50.59% that is very close to the ideal value of 50%. In the ADC mode, this design achieves an ENOB of 9.66 under 20 MS/s.

This paper presents a 4-channel 8-bit 1.6-GS/s Flash assisted SAR Time-Interleaved ADC in 40-nm CMOS. Putting all channel mismatch including offset, gain and timing- skew into consideration. Modified bootstrap circuit used to inhibit timing-skew; background offset calibration without complicated circuit performed in the analog domain. Proposed background gain calibration detects signal which correlated with gain error in SAR ADC and correct gain mismatch by simple calibration capacitor array, which only increase a little power and area overhead. Hybrid architecture has been adopted in this chip. Owing to Flash-SAR operation, single channel's speed and overall energy efficient can be promote at the same time. The calibration enhance SNDR from 34.59-dB to 44.15-dB. Moreover, this design consumes 16.76mW under 1V supply with FoM of 78.93fJ/conv-step in the measurement.

This paper presents a new post-processing method to estimate the real bit error rate (BER) of successive approximation register (SAR) analog-to-digital converters (ADCs) based on the conventional test scheme. Conventional testing method acquires BER based on difference between two measured output codes, rather than between a measured output code and its corresponding ideal one. This makes the resulting BER have a wrong trend with increasing sampling speed of ADC. Therefore, this work analyzes the difference between these two cases and proposes a simple post-processing method to obtain a more realistic BER based on the conventional BER test scheme. The experimental results demonstrate the proposed method can effectively obtain the correct BER trend for a SAR ADC.

This paper presents a 4x-interleaved 8b 2-GS/s Flash-SAR ADC in 40-nm CMOS. Instead of adding complicated circuits to calibrate offset in the background, we proposed a “top-plate swapping” technique, which only requires a low complexity circuit, to deal with offset mismatches among the channels. With the aid of the Flash ADC, a single channel can achieve 500MS/s. Proper redundancy is manipulated to deal with gain mismatches and comparator offsets among the Flash ADC and the SAR sub-ADCs. A global master clock is adopted to mitigate the impact of timing-skew. The proposed calibration enhances SNDR from 37.34-dB to 47.81-dB. Moreover, this design consumes 17.84mW under a 0.9V supply with a FoM of 44.41fJ/conv-step in post-layout simulation.

This paper presents a 2x-interleaved 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC) that performs 9.73 ENOB under 1-GS/s in 40nm with post-layout simulation. A bootstrapped switch circuit is proposed for 2x-interleaved structure using global master clock without any timing-skew calibration. In each channel, a sub-range SAR ADC sharing a common coarse SAR ADC with loop-unrolling technique is proposed to enhance speed. This ADC consumes 9.02mW with a figure of merit (FoM) of 10.6fJ/conv-step in post-layout simulation and only covers an area of 0.096mm2.

This paper presents a 0.35 V 100 kS/s 10-bit successive approximation register (SAR) ADC with adaptive window (AW) in 90 nm CMOS. The SAR ADC uses the transient information of the latch comparator to create redundancy ranges. Furthermore, the proposed technique also uses the transient information to produce AW for each bit which can significantly reduce the power consumption of the comparator, the DAC settling time and also digital control logic. Last but not least, the timing control window can also avoid ADC from encountering meta-stability. The measurement result achieves an SNDR of 57.18 dB, an ENOB of 9.2 bits, a power consumption of 74 nW, and a resulting FoM of 1.25 fJ/conv.-step.

This paper presents a new circuit technique named as “residue oversampling,” which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying dynamic element matching (DEM), the impacts of capacitor mismatch and noise upon the successive-approximation register (SAR) ADCs are diminished significantly without calibrations. The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise-and-distortion ratios (SNDRs) are 66.84 dB and 69.78 dB, respectively.

This paper presents a novel low power duobinary voltage mode transmitter in 90-nm CMOS process for wireline communication. As a matter of fact, voltage mode transmitters potentially save much more power than current mode transmitters. By adding a medium level, a half supply voltage, to conventional NRZ voltage mode transmitters, duobinary coding can simply be achieved. Post-layout simulation demonstrates the architecture with a new preemphasis method dissipates approximately 16.35 mW from a 1.0 V supply when transmitting 8 Gb/s 1.0 V differential amplitude data with 2-tap pre-emphasis, achieving 2.04 pJ/bit energy efficiency.

Simulating/Measuring the jitter tolerance of clock and data recovery (CDR) circuits, and confirming if the associated jitter tolerance meets the required specification for a specified communication standard, is an important consideration for designing/testing high-speed serial link interface circuits. However, conducting such performance evaluations are costly and time-consuming. In this paper, a simple but effective testing method for evaluating the tracking capability of bang-bang CDR circuits is introduced. The tracking capability of the CDR loop is obtained by simply inverting the recovered clock to produce a 0.5 unit interval (UI) phase shift and capture the tracking time. The proposed technique is easily implemented, because of its fully-digital characteristic, and suitable for testing CDRs that is embedded in a complex interface transceiver. Then, a quick jitter tolerance estimation technique based on the obtained tracking capability is proposed to simplify the time-consuming process as well as avoid the costly test equipment required for designing and/or testing CDR circuits. Experimental results show that the proposed techniques could precisely evaluate the tracking capability and efficiently reduce test costs in acquiring complete jitter tolerance testing.

This paper proposes a splittable amplifier technique that can be either decomposed into two identical halves or merged for enhancing the utilization of the amplifier power and alleviating the memory effect, when applying operational amplifier (opamp) sharing. In a two-phase clock system, the amplifier can be split into two identical small amplifiers in one phase simultaneously for use in two circuits. Next, the two small amplifiers can be merged into one amplifier in the other phase for usage in another circuit. Compared with the conventional opamp sharing, a more power-efficient amplifier arrangement is achieved in the split mode. In this paper, three individual sample-and-hold (S/H) circuits with the proposed technique are designed to demonstrate the efficiency of memory effect cancellation. The simulations show that in contrast to the output spectrum of two S/H circuits with conventional opamp sharing, the spurious tones due to the memory effect can be suppressed by at least 14.66 dB in the split mode and at least 7.32 dB in the combination mode with a 0.6-VP-Pinput signal when using the proposed technique.

A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.

In comparison with conventional operational amplifier, ring amplifier can achieve better power efficiency for switched capacitor circuits. However, the cascade-inverter architecture of ring amplifier may suffer from undesirable oscillation which has a great impact on transient stability. This paper presents a latched-based ring amplifier which is capable of decreasing the probability of oscillation. Besides, two auto-zero schemes are employed in different pipelined stages to reduce the common-mode voltage offset and to increase the stability. The prototype ADC was fabricated in a 90-nm CMOS technology. The measured SNDR and SFDR are 52.06 dB and 63. 15 dB, respectively, for a Nyquist frequency input sampled at 35 MS/s, and the ADC consumes 3.65 mW.

As technology advances, power consumption becomes a big challenge in modern very large-scale integration designs. To resolve this problem, power-gated technology has been widely adopted in circuit designs. Since the turn-on sequence of power switches has a great impact on the rush current, wake-up, and sequence times of a power gating design, this paper proposes a methodology to construct a hybrid routing structure to connect power switches. Our hybrid routing structure can induce less rush current and satisfy timing constraints because a better daisy chain is constructed. To find members of the daisy chain, an integer linear programming algorithm is used to pick up suitable power switches. To determine suitable depth of a daisy chain, we propose a model for a power gating design and induct precise equations to estimate voltage and rush current equations according to the model. All of our experiments are based on industrial designs and measured by vendor tools. The experimental results demonstrate the efficiency and effectiveness of our design methodology.

Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used in biomedical and portable/wearable electronic systems due to their excellent power efficiency. However, both the design and the optimization of high-performance SAR ADCs are time consuming, even for well-experienced circuit designers. For system designers, it is also hard to quickly evaluate the feasibility of a given specification in a process node. This paper presents a systematic sizing procedure for asynchronous SAR ADCs based on design considerations. A sizing tool based on the proposed design procedure is also implemented, the sizing results of which are highly competitive in comparison with other state-of-the-art manual works. Moreover, the sizing time is relatively short due to the efficient and effective search algorithms employed. In addition to the simulation results, two silicon proofs with different specifications and process nodes are provided to demonstrate the feasibility of this design methodology.

This paper presents a low-power energy-harvesting circuit with error-correction demodulation for radio-frequency identification (RFID) application. This circuit uses the new structure to demodulate ASK signals and includes the power unit with a wake-up circuit and a power-on-reset controller. The energy-harvesting circuit proposed by this paper can substantially decrease the capacitance used in the demodulator circuit and the wake-up circuit, and the capacitance is 14 pF only. Moreover, a detection circuit and a correcting circuit are adopted to enhance bit error rate of decoding. The chip was implemented in CMOS 0.18 μm technology. The sensitivity of this work is -13 dBm. The pulse width error can be reduced to less than 1% to fit the EPC Gen-2 standard by error-correction demodulator.

The analog-to-digital converter (ADC) is an essential component providing the interface between the sensed analog signal and the corresponding digital representation for a portable ultrasonic systems. In order to extend the battery life for the portable system, a low-voltage ADC is crucial for saving the power. However, the sensed analog signal is usually larger than the tolerable range of a low-voltage ADC. A level shifter, which possibly consumes more power than ADC, is therefore adopted to solve this problem. This paper presents a 10-bit 50-MS/s successive approximation register (SAR) ADC by manipulating simple but effective circuit design techniques to operate at dual-voltage domain without the need of an additional level shifter for shrinking the input signals. Particularly, we propose a technique to implement the ADC with 3.3-V I/O devices and 1.2V MOS transistors. The proof-of-concept design was fabricated in TSMC 130-nm 1P8M CMOS technology. It consumes 1.6 mW at a 50 MS/s sampling frequency and about 2 MHz sinusoidal input signal with 1.65V input common-mode voltage and 2Vp-p differential input amplitude. The measurement result shows an ENOB of 9.15 bits, and both the DNL and INL are within 1 LSB. The active area is 0.226 mm2.

This paper proposes a 10-bit SAR ADC with time-based fixed window to reduce the unnecessary capacitor switchings, comparisons and digital control operations. It used only one comparator, and no need additional reference voltage to create the window. At 0.5-V supply and 100-kS/s, the ADC consumes only 252 nW and achieves an SNDR of 57.96 dB, resulting in a FOM of 3.9 fJ/conversion-step. The ADC core occupies an active area of only 178 × 184 μm2in 0.18-μm CMOS process.

This paper presents a 3.2 Gb/s low-power clock and data recovery (CDR). The improved architecture using two half-rate gated voltage-controlled oscillators (GVCOs) shared between frequency presetting and data recovery modes is presented to remove the LC-tank voltage-controlled oscillator in a cascaded CDR. Moreover, using the proposed active inductive loading technique instead of the on-chip inductor reduces the power consumption and area in high-speed operation. This CDR circuit has been designed in TSMC 0.18 μm CMOS technology. It consumes 22.5 mW from a 1.8-V supply and occupies an active area of 0.26 mm2. The peak-to-peak and rms jitter of the recovered clock are 95.6 ps and 12.1 ps for a 3.2 Gb/s 27-1 PRBS, respectively.

This paper proposes a 3rd-order low-distortion delta-sigma modulator (DSM) structure, which uses the timing-sharing technique between the 2nd and 3rd integrators during one clock phase. Further, since the operation phase of the 1st integrator is different to those of the 2nd and 3rd integrators, the three integrators are realized in just single opamp by the opamp sharing. Therefore, the power consumption can be reduced greatly. Besides, the proposed DSM structure poses the feature of relaxed feedback timing. The quantization and DEM operation can be extended from a non-overlapping interval for a conventional low-distortion structure to half of the clock period. The proposed 3rd-order 4-bit DSM is implemented in a 90-nm CMOS process. Post-layout simulation shows that the modulator achieves 75.1-dB SNDR with 2.5-MHz input signal bandwidth and 80-MHz sampling frequency. The power consumption is only 1.42 mW with 61.1-fJ/conversion-step FOM, and the core area is 683 × 592 μm2.

This brief presents a 10-bit 30-MS/s successive-approximation-register analog-to-digital converter (ADC) that uses a power efficient switchback switching method. With respect to the monotonic switching method, the input common-mode voltage variation reduces which improves the dynamic offset and the parasitic capacitance variation of the comparator. The proposed switchback switching method does not consume any power at the first digital-to-analog converter switching, which can reduce the power consumption and design effort of the reference buffer. The prototype was fabricated in a 90-nm 1P9M CMOS technology. At 1-V supply and 30 MS/s, the ADC achieves an sequenced neighbor double reservation of 56.89 dB and consumes 0.98 mW, resulting in a figure-of-merit (FOM) of 57 fJ/conversion-step. The ADC core occupies an active area of only 190 × 525 μm2.

Power has become a burning issue in modern VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. Given a design, we can reduce its power consumption by replacing some flip-flops with fewer multi-bit flip-flops. However, this procedure may affect the performance of the original circuit. Hence, the flip-flop replacement without timing and placement capacity constraints violation becomes a quite complex problem. To deal with the difficulty efficiently, we have proposed several techniques. First, we perform a co-ordinate transformation to identify those flip-flops that can be merged and their legal regions. Besides, we show how to build a combination table to enumerate possible combinations of flip-flops provided by a library. Finally, we use a hierarchical way to merge flip-flops. Besides power reduction, the objective of minimizing the total wirelength is also considered. The time complexity of our algorithm is Θ(n1.12) less than the empirical complexity of Θ(n2). According to the experimental results, our algorithm significantly reduces clock power by 20-30% and the running time is very short. In the largest test case, which contains 1 700 000 flip-flops, our algorithm only takes about 5 min to replace flip-flops and the power reduction can achieve 21%.

Switched capacitors are commonly used in analog design. The circuit performance based on this technique relies on the accuracy of capacitance ratios, which are affected by random and systematic mismatches. To meet the accuracy requirement, designers can increase the layout area of unit capacitors to reduce random mismatch. Since increasing layout area enlarges the distance between unit capacitors, it induces more gradient errors, which results in larger systematic mismatch. Therefore, the better way for reducing the gradient errors is to carefully determine the locations of unit capacitors in a capacitor array. Moreover, the resulting placement must have high capacitance correlation in order to enhance yield. In this paper, we first explore the attributes of a good capacitor placement, which can reduce gradient errors and increase capacitance correlation. Then, an analytical-based approach is proposed to complete capacitor placement considering these issues. Finally, the results are optimized by arbitrarily swapping two unit capacitors. Compared with the simulated annealing based approach, the proposed method not only achieves better placement results but also gets 34x faster for the largest benchmark capacitor array.

Analog-to-digital converter (ADC) is a vital component for modern electronic systems, but designing an ADC usually takes much time and effort. Though several synthesis methods have been presented for analog circuits, there exists limited works focusing on ADC design automation. In this paper, we propose a systematic sizing methodology to minimize the power consumption for successive approximation register (SAR) ADCs in transistor level. This method manipulates the characteristics of SAR ADC to develop an efficient searching algorithm for shortening the sizing time. The time complexity of our method is O(2 log2|S|), where jSj is the number of candidates in the searching space. According to the proposed sizing flow, we develop a sizing tool which is independent of manufacturing process and is able to minimize power consumption for SAR ADCs. By using the developed sizing tool, a proof-of-concept prototype was carried out within only 15 minutes and fabricated in a 1P4M 0.11μm process. The measurement results show the prototype demonstrates a high competitiveness compared to other state-of-the-art works on performance and power efficiency.

To obtain good layout quality and reliability, placement is a very important stage during the physical design of analog circuits. Many works have been proposed to consider topological constraints for analog placement, and they devote to generate compact placements to minimize area and wirelength. However, a compact placement may induce unwanted routing issues. In order to reduce parasitics and cross-talk effects during the routing phase, wires are preferred not to pass above the active area of analog devices. Therefore, it is required to preserve enough routing spaces between devices for successful routing. Currently, there exists limited works studying routability for analog placement, but none of these works consider that symmetry property must be maintained during placement expansion. In this paper, we present a two-stage routability-driven analog placer based on ASF-B*-tree and HB*-tree representations. To reduce running time, our placement algorithm first generates a compact placement to minimize wirelength and area without considering congestion problem. Then, routing congestion regions are expanded locally to resolve the routability problem. Most importantly, the symmetry property of analog placement is always satisfied during the expansion process. Experimental results show that our analog placer can effectively minimize routing congestion without violating the symmetry property after placement expansion.

Switched capacitors are commonly used in analog circuits to increase the accuracy of analog signal processing and lower power consumption. To take full advantage of switched capacitors, it is very important to achieve accurate capacitance ratios in the layout of the capacitor arrays, which are affected by systematic and random mismatches. A good capacitor placement should have a common-centroid structure with the highest possible degree of dispersion to mitigate mismatches. Several dummy units should be inserted to make the placement shape more square and compact. This paper proposes a simulated-annealing-based approach for mismatch-aware common-centroid placement under the above constraints. A pair-sequence representation is used to record a placement, and a couple of associated operations are developed to find better solutions. The experimental results show that the proposed placements achieve smaller oxide-gradient-induced mismatch and larger overall correlation coefficients (i.e., higher degree of dispersion) than those of previous works.

One of the most important issues during the analog layout phase is to achieve accurate capacitance ratios. However, systematic and random mismatches will affect the accuracy of the capacitance ratios. A common-centroid placement is helpful to reduce the systematic mismatch, but it still needs the property of high dispersion to reduce the random mismatch [10]. To deal with this problem, we propose a simulated annealing [15] based approach to construct a common-centroid placement which exhibits the highest possible degree of dispersion. To facilitate this framework, we first propose the pair-sequence representation to represent a common-centroid placement. Then, we present three operations to perturb the representation, which can increase the degree of dispersion without breaking the common-centroid constraint in the resulting placement. Finally, to enhance the efficiency of our simulated annealing based approach, we propose three techniques to speed up our program. The experimental results show that our placements can simultaneously achieve smaller oxide-gradient-induced mismatch and larger overall correlation coefficients (i.e., higher degree of dispersion) than [10] in all test cases. Besides, our program can run much faster than [10] in larger benchmarks.

A transition-code based method is proposed to reduce the linearity testing time of pipelined analog-to-digital converters (ADCs). By employing specific architecture-dependent rules, only a few specific transition codes need to be measured to accomplish the accurate linearity test of a pipelined ADC. In addition, a simple digital Design-for-Test (DfT) circuit is proposed to help correctly detect transition codes corresponding to each pipelined stage. With the help of the DfT circuit, the proposed method can be applied for pipelined ADCs with digital error correction (DEC). Experimental results of a practical chip show that the proposed method can achieve high test accuracy for a 12-bit 1.5-bit/stage pipelined ADC with different nonlinearities by measuring only 9.3% of the total measured samples of the conventional histogram based method.

To reduce parasitic mismatches in analog design, we usually care about the property of symmetric placement for symmetry groups, which would form several symmetry islands in a chip. However, routing is greatly affected by placement results. If modules with input or output ports are placed arbitrarily in a symmetry island, the routing wires, which connect these modules with other modules outside the island, may induce unwanted parasitics coupling to signals, and thus circuit performance is deteriorated. This phenomenon can not be identified by a cost function, which only considers placement area and total wire length. Therefore, we would like to introduce the necessity of considering boundary constraint for the modules with input or output ports in symmetry islands. Based on ASF-B* tree [3], we explore the feasible conditions for 1D and 2D symmetry islands to meet this constraint. Further, a procedure is presented to maintain the feasibility for each ASF-B* tree after perturbation. Experimental results show that our approach guarantees the boundary property for the modules with input or output ports in symmetry islands.

In high-speed Flash analog-to-digital converters (ADCs), preamplifiers are often placed in front of a comparator to reduce metastability errors and enhance comparison speed. The accuracy of a Flash ADC is mainly limited by the random offsets of preamplifiers and comparators. This paper presents a 5-b Flash ADC with a digital random offset calibration scheme. For calibration, programmable resistive devices are used as the loading devices of the second-stage preamplifiers. By adjusting the calibration resistors, the input-referred offset voltage of each comparator is reduced to be less than 1/2 LSB. Fabricated in a 0.13-¿m CMOS process, experimental results show that the ADC consumes 120 mW from a 1.2-V supply and occupies a 0.18- mm2active area. After calibration, the peak differential non-linearity (DNL) and integral non-linearity (INL) are 0.24 and 0.39 LSB, respectively. At 3.2-GS/s operation, the effective number of bits is 4.54 b, and the effective resolution bandwidth is 600 MHz. This ADC achieves figures of merit of 3.07 and 4.30 pJ/conversion-step at 2 and 3.2 GS/s, respectively.

A built-in self-test (BIST) circuit for jitter measurement is proposed. The BIST circuit contains an improved cyclic time-to-digital converter (TDC) to achieve 6-ps resolution, and a pulse amplifier (PA) in front of the cyclic TDC to equivalently enhance timing resolution to 0.6 ps. The quantity of jitter is derived by analyzing the digital output codes of the BIST circuit. The input frequency range of the signal-under-test (SUT) is from 200 MHz to 2 GHz for 0.6-ps timing resolution, and from 100 Hz to 2 GHz for 6-ps timing resolution. In addition to the wide input frequency range and fine resolution, the proposed BIST reduces testing time maximally by 95 % in comparison with the conventional BIST circuit based on component-invariant vernier delay line TDC. The presented BIST circuit occupies 0.6 × 0.336 mm2in a 0.18-um CMOS process.

In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would cause large linearity test error when the reduced code based method is applied to a pipelined ADC with the DEC technique. In order to overcome this problem, a simple digital design-for-test (DfT) circuit is proposed. Simulation results demonstrate the effectiveness of the refined reduced code based method combined with the proposed DfT circuit.

In this work, a characteristic observation method is proposed to reduce the test time for the INL and DNL testing of a pipelined A/D converter. The symmetrical and specific regular rules are concluded by analyzing the characteristic of a pipelined ADC. As a result, based on the specific rules, only a few code bin widths of specific codes should be measured to accomplish the accurate full-code INL/DNL testing for a pipelined ADC. Simulation results show that the full-code INL/DNL performance of a 10-bit pipelined ADC can be characterized by measuring code bin widths of 33 codes only in our proposed method.

An improved histogram testing method for analog-to-digital converters (ADCs) is proposed. The proposed method reveals not only the static performance but also the dynamic ones, such as the effective number of bits (ENOB) with a sinusoidal input signal. Therefore, single histogram testing is performed rather than using both the histogram and spectral methods to reduce the total test cost. The proposed testing method was experimentally validated on a commercial 8-bit ADC to demonstrate it effectiveness. The experimental result indicated that the proposed histogram-based test method exhibits a good agreement to the measured results of the classical FFT-based method

In this paper, a pipelined analog-to-digital converter (ADC) which employs a modified time-shifted correlated double sampling (CDS) technique is proposed. The conventional time-shifted CDS technique can significantly reduce the errors due to the finite gain of the operational amplifier (op-amp) without compromising the conversion speed. However, it needs a high-linearity op-amp to realize the front-end sample-and-hold (SHA) such that the sampled signal without being distorted too much. In order to relax the high-linearity requirement of the op-amp, a new type of SHA circuit is presented

In this paper, we propose two novel dual edge-triggered flip-flops. One design eliminates redundant transitions of internal nodes when current data is the same as the previous one. This has the least power delay product compared to other dual edge-triggered flip-flops in all range of possible data switching activity and its delay is also the smallest. The other proposed flip-flop disables internal clocked transistors. When data switching activity is within 20%, it has the least power consumption.

Pipelined A/D converters have intrinsic high-speed characteristics and are widely used in wideband communication and video systems. In this paper, we propose a low-cost diagnosis methodology for pipelined A/D converters which employs three techniques in the diagnosis process: (1) time-division-multiplexing (TDM), (2) scan based testing, and (3) VCO based measurement. The last technique is developed to diagnose the most critical mixed-signal functional blocks in the pipelined ADC including the sample-and-hold amplifier (SHA) and the digital-to-analog sub-converters (DASC). It provides a great capability to distinct signals with very small voltage difference and is insensitive to process variations and immune to noise induced errors. The diagnosis methodology is power- and area-efficient because it only needs low-complexity and low-area BIST circuits to accomplish the full diagnosis process. A 12-bit pipelined A/D converter with the proposed diagnosis scheme is designed and simulated using the TSMC 0.25um 1P5M technology to demonstrate the effectiveness of the proposed methodology.

In this paper, a built-in self-test (BIST) methodology used to test the important transmission parameters, signal-to-noise-and-distortion (SNDR) and effective number of bits (ENOB), of analog-to-digital converters (ADCs) is proposed. A sigma-delta modulation based signal generator is presented which can concurrently produce high frequency analog sinusoidal test stimuli and digital sinusoidal reference signals on chip. Unlike conventional test methods which compute these parameters based on the spectrum information after fast Fourier transformation (FFT), the presented BIST scheme can directly determine the noise-and-distortion power density and SNDR in time domain. It can reduce the high cost of implementing FFT and windowing functional blocks, and alleviate the difficulty in setting the test frequencies and measurement conditions.

In this paper, a built-in self test (BIST) methodology to measure the four key parameters of A/D converters, namely offset error, gain error, integral nonlinearity error and differential nonlinearity error is proposed. A sigma-delta modulation based signal generator is presented which can concurrently produce analog sinusoidal test stimuli and digital sinusoidal reference signals on chip. By comparing the sinusoidal histogram of the ADC output signals with that of the generated reference digital signals, the parameters can be determined on chip based on some previously-derived equations. This BIST scheme has the following advantages: (1) high accuracy; (2) parameter measurement capability for different frequencies; (3) dynamic sinusoidal testing capability; and (4) low chip area overhead. An 8 bit A/D converter with the proposed BIST architecture is designed and simulated using the TSMC 0.35 /spl mu/m 1P4M technology. The simulation results show that the test accuracies for the four parameters are all within 0.05 LSB.

In this paper, the optimum functional patterns for CMOS operational amplifier are proposed based on an analysis to find the maximum difference between the good circuit and the faulty circuit for a CMOS operational amplifier. The theoretical and simulation results show that the derived test patterns do give the maximum difference at the output even when the circuit has a "soft" fault. The results have also been applied to generate test patterns for a programmable gain/loss mixed signal circuit.