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Joosun Hahn

dblp:86/2470 · DBLP profile ↗
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5ranked-venue papers
1as first author
0since 2021 · last 2002
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 2Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Embedded and real-time systems · 86% Memory systems · 14%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Embedded and real-time systems › real-time scheduling › worst-case analysis
cache-related preemption delay
0.142001
Bounding Cache-Related Preemption Delay for Real-Time Systems · IEEE Trans. Software Eng. 2001
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemtive Scheduling · IEEE Trans. Computers 1998
Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling · RTSS 1997
Embedded and real-time systems
real-time scheduling
0.142001
Bounding Cache-Related Preemption Delay for Real-Time Systems · IEEE Trans. Software Eng. 2001
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemtive Scheduling · IEEE Trans. Computers 1998
Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling · RTSS 1997
Embedded and real-time systems › real-time scheduling
schedulability analysis
0.132001
Bounding Cache-Related Preemption Delay for Real-Time Systems · IEEE Trans. Software Eng. 2001
Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling · RTSS 1997
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling · RTSS 1996
Embedded and real-time systems › real-time scheduling › fixed-priority scheduling
fixed-priority preemptive scheduling
0.131998
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemtive Scheduling · IEEE Trans. Computers 1998
Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling · RTSS 1997
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling · RTSS 1996
Memory systems
cache
0.122001
Bounding Cache-Related Preemption Delay for Real-Time Systems · IEEE Trans. Software Eng. 2001
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemtive Scheduling · IEEE Trans. Computers 1998
Embedded and real-time systems › real-time scheduling › schedulability analysis
response time analysis
0.021997
Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling · RTSS 1997
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling · RTSS 1996

Methods — techniques the papers use, named apart from their topics

linear programming · 0.1fixed-priority scheduling · 0.0response time analysis · 0.0
YearPublicationVenuePosition
2002 Analysis of Worst Case DMA Response Time in a Fixed-Priority Bus Arbitration Protocol
Joosun Hahn, Rhan Ha, Sang Lyul Min, Jane W.-S. Liu
Real Time Syst.1
2001 Bounding Cache-Related Preemption Delay for Real-Time Systems
abstract
Cache memory is used in almost all computer systems today to bridge the ever increasing speed gap between the processor and main memory. However, its use in multitasking computer systems introduces additional preemption delay due to the reloading of memory blocks that are replaced during preemption. This cache-related preemption delay poses a serious problem in realtime computing systems where predictability is of utmost importance. We propose an enhanced technique for analyzing and thus bounding the cache-related preemption delay in fixed-priority preemptive scheduling focusing on instruction caching. The proposed technique improves upon previous techniques in two important ways. First, the technique takes into account the relationship between a preempted task and the set of tasks that execute during the preemption when calculating the cache-related preemption delay. Second, the technique considers the phasing of tasks to eliminate many infeasible task interactions. These two features are expressed as constraints of a linear programming problem whose solution gives a guaranteed upper bound on the cache-related preemption delay. This paper also compares the proposed technique with previous techniques using randomly generated task sets. The results show that the improvement on the worst-case response time prediction by the proposed technique over previous techniques ranges between 5 percent and 18 percent depending on the cache refill time when the task set utilization is 0.6. The results also show that as the cache refill time increases, the improvement increases, which indicates that accurate prediction of cache-related preemption delay by the proposed technique becomes increasingly important if the current trend of widening speed gap between the processor and main memory continues.
Chang-Gun Lee, Kwangpo Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim
IEEE Trans. Software Eng.3
1998 Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemtive Scheduling
abstract
We propose a technique for analyzing cache-related preemption delays of tasks that cause unpredictable variation in task execution time in the context of fixed-priority preemptive scheduling. The proposed technique consists of two steps. The first step performs a per-task analysis to estimate cache-related preemption cost for each execution point in a given task. The second step computes the worst case response time of each task that includes the cache-related preemption delay using a response time equation and a linear programming technique. This step takes as its input the preemption cost information of tasks obtained in the first step. This paper also compares the proposed approach with previous approaches. The results show that the proposed approach gives a prediction of the worst case cache-related preemption delay that is up to 60 percent tighter than those obtained from the previous approaches.
Chang-Gun Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim
IEEE Trans. Computers2
1997 Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling
abstract
We propose an enhanced technique for analyzing, and thus bounding cache related preemption delay in fixed priority preemptive scheduling focusing on instruction caching. The proposed technique improves upon previous techniques in two important ways. First, the technique takes into account the relationship between a preempted task and the set of tasks that execute during the preemption when calculating the cache related preemption delay. Second, the technique considers phasing of tasks to eliminate many infeasible task interactions. These two features are expressed as constraints of a linear programming problem whose solution gives a guaranteed upper bound on the cache related preemption delay. The paper also compares the proposed technique with previous techniques. The results show that the proposed technique gives up to 60% tighter prediction of the worst case response time than the previous techniques.
Chang-Gun Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim
RTSS2
1996 Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
abstract
We propose a technique for analyzing cache-related preemption delays of tasks that cause unpredictable variation in task execution time in the context of fixed-priority preemptive scheduling. The proposed technique consists of two steps. The first step performs a per-task analysis to estimate cache-related preemption cost for each execution point in a given task from the number of useful cache blocks at the execution point. The second step computes the worst case response time of each task using a response time equation and a linear programming technique which takes as its input the preemption cost information of tasks obtained in the first step. Our experimental results show that the proposed technique gives a prediction of the worst case cache-related preemption delay that is up to 60% tighter than that obtained from previous approaches.
Chang-Gun Lee, Joosun Hahn, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim
RTSS2