The processing-using-memory (PUM; a.k.a. inmemory computing) paradigm aims to eliminate data movement energy and performance costs by using memory cell interactions to directly perform computation. Given PUM's potential for large savings, prior works have proposed many different datapath microarchitectures to demonstrate how general-purpose PUM benefits a wide range of application kernels. Unfortunately, these efforts largely depend on microarchitecture-specific vector-like interfaces that (1) force many of an application's operations to be offloaded to a CPU, (2) require significant programmer effort to scale up applications to an entire memory chip, and (3) make it impractical to develop badly-needed systems software and programming tools for PUM. To address these three issues, we propose the memory processing unit (MPU), a microarchitecture-agnostic interface layer for general-purpose PUM with three components. First, we develop an MPU instruction set architecture (ISA) with instructions to facilitate application scaling and task coordination. Second, we propose an ensemble execution model that coordinates execution across millions of PUM vector function units and maps to most general-purpose PUM microarchitectures. Third, we design a comprehensive MPU control path that efficiently executes MPU ISA binaries across multiple ensembles, and can enable CPU-free execution of complex end-to-end applications with PUM. We demonstrate how the MPU maps to multiple previously-proposed PUM datapaths, and how it achieves average performance/energy improvements of$\mathbf{1. 7 9} \times \boldsymbol{/} \mathbf{3. 2 3} \times$for$\mathbf{2 1}$data-intensive kernels over these prior works ($67 \times / 47 \times$vs. a modern GPU), while also achieving performance and energy improvements for the complex end-to-end applications.

To combat the high energy costs of moving data between main memory and the CPU, recent works have proposed to perform processing-using-memory (PUM), a type of processing-in-memory where operations are performed on data in situ (i.e., right at the memory cells holding the data). Several common and emerging memory technologies offer the ability to perform bitwise Boolean primitive functions by having interconnected cells interact with each other, eliminating the need to use discrete CMOS compute units for several common operations. Recent PUM architectures extend upon these Boolean primitives to perform bit-serial computation using memory. Unfortunately, several practical limitations of the underlying memory devices restrict how large emerging memory arrays can be, which hinders the ability of conventional bit-serial computation approaches to deliver high performance in addition to large energy savings.

This tutorial provides students with a basic understanding of the challenges involved in designing RF-powered RF-connected integrated circuits (ICs) with on-chip antennas (OCAs). The tutorial begins by discussing the potential cost and performance advantages of creating ICs with OCAs. The design of ICs in which the antenna and conventional circuitry are all fabricated on the same substrate offers advantages in terms of size, weight and cost over conventional RFID/sensor systems in which an IC is assembled onto an antenna substrate; however, it is challenging because the limited size of the antenna set by the die size and its proximity to a resistive ground plane (the IC substrate) both decrease the RF energy that can be harvested to operate the on-chip circuitry. In this Tutorial, we will apply simplifying approximations in order to develop basic equations relating the size and geometry of the antennas to the ability of the OCA-IC to harvest ambient RF energy; and, we will validate those equations with electromagnetic field simulations. The tutorial will also examine the challenging issue of matching the antenna to the on-chip electronics in a way that maximizes the power that can be extracted from an external RF signal. The Tutorial will consider operation across a range of frequencies and will explore both in-plane spiral antennas and out-of-plane helical antennas. The Tutorial will conclude with an analysis of the case when an OCA-ICs is integrated into medicines in order to provide secure validation of medicinal pills and capsules.

Network analytics are widely used in many fields. Increasingly though, the networks of interest are high dimensional. Rather than just focusing on the traditional who is interaction with whom networks, modern network analysis examines the who, what, where, when and why ecology of relations. For example, studies of organizations might look at the social network within the organization as well as the task assignment and knowledge network. Studies using Twitter frequently look at the mentions network at the same time as the hashtag network. Making network science actionable typically involves answering questions about where the network is concentrated or how the network varies over time. This tutorial will cover the basics of Network analytics and demonstrate the use of ORA to support social media analytics using high dimensional network analytics and visualization for social media networks, semantic networks, geo-spatial networks, and dynamic networks. It will cover the basics of visualizing and analyzing time varying networks and spatially positioned networks. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author. ORA is a powerful network analysis and visualization tool (Carley, 2017). ORA supports the assessment of standard social network data, organizational network data, high-dimensional network data, meta-network data, geo-spatial network data, and dynamic network data.

Predicting countries that will seek bioweapons (BW) enables the international community to act early in order to prevent these countries from acquiring such weapons. Unfortunately, the literature on countries' BW programs mainly consists of case studies that focus on one or a few countries. Although case studies are valuable, they are typically not predictive. Moreover, case studies require substantial effort and expertise, and are thus unfeasible for all countries. In this paper, we develop a computational methodology that predicts countries that will seek BW. Our methodology consists of a sociocultural model and indicators that computationally capture expert opinions about why and how countries acquire BW. Our methodology systematically examines all countries in the world and can be used by non-BW experts based on publicly available data. We validate our methodology by examining the methodology's ability to predict historical BW proliferators.

Automation of data collection using online resources has led to significant changes in traditional practices of social network analysis. Social network analysis has been an active research field for many decades; however, most of the early work employed very small datasets. In this paper, a number of issues with traditional practices of social network analysis in the context of dynamic, large-scale social networks are pointed out. Given the continuously evolving nature of modern online social networking, we postulate that social network analysis solutions based on incremental algorithms will become more important to address high computation times for large, streaming, over-time datasets. Incremental algorithms can benefit from early pruning by updating the affected parts only when an incremental update is made in the network. This paper provides an example of this case by demonstrating the design of an incremental closeness centrality algorithm that supports efficient computation of all-pairs of shortest paths and closeness centrality in dynamic social networks that are continuously updated by addition, removal, and modification of nodes and edges. Our results obtained on various synthetic and real-life datasets provide significant speedups over the most commonly used method of computing closeness centrality, suggesting that incremental algorithm design is a fruitful research area for social network analysts.

The increasing availability of dynamically growing digital data that can be used for extracting social networks has led to an upsurge of interest in the analysis of dynamic social networks. One key aspect of social network analysis is to understand the central nodes in a network. However, dynamic calculation of centrality values for rapidly growing networks might be unfeasibly expensive, especially if it involves recalculation from scratch for each time period. This paper proposes an incremental algorithm that effectively updates betweenness centralities of nodes in dynamic social networks while avoiding re-computations by exploiting information from earlier computations. Our performance results suggest that our incremental betweenness algorithm can achieve substantial performance speedup, on the order of thousands of times, over the state of the art, including the best-performing non-incremental betweenness algorithm and a recently proposed betweenness update algorithm.

Outphasing power amplifiers (PAs) with power reclamation networks are an attractive solution for maintaining a constant PA load during outphasing while minimizing energy lost. Power reclamation networks have only been demonstrated at frequencies below 2 GHz. In this work, we examine power reclamation networks for outphasing PA topologies and investigate how their efficiency scales with frequency. Our results show that at mm-wave frequencies, power reclamation network efficiency is dominated by the current in the resonant portion of the rectifier and that this loss can increase disproportionately with frequency, thus placing a key limitation on the efficiency of power reclamation networks at mm-wave frequencies.

The capability to build nuclear weapons is a key national security factor that has a profound influence on the balance of international relations. In addition to longstanding players, regional powers and peripheral countries have sought for ways of acquiring and/or developing them. The authors postulate that to express the capabilities, relative positions, and interrelations of the countries involved in the production of nuclear weaponization knowledge, dynamic network analysis provides valuable insight. In this article, the authors use a computational framework that combines techniques from dynamic network analysis and text mining to mine and analyze large‐scale networks that are extracted from open theoretical and experimental nuclear research publications of the last two decades. More specifically, they build interlinked, dynamic networks that model relationships of nuclear researchers based on the open literature and supplement this information with text mining to classify the nuclear weaponization capabilities of each publication—of each author, organization, city, and country. Using such a comprehensive computational framework, they are able to (a) elicit the hot topics in nuclear weaponization research, (b) assess the nuclear expertise level of each country, (c) differentiate between established and emergent players, and (d) identify the key entities at various levels such as organization, city, and country.

An electrical and physical synthesis flow for high-speed analog and radio-frequency circuits is presented in this paper. Novel techniques aiming at fast parasitic closure are employed throughout the flow. Parasitic corners generated based on the earlier placement statistics are included for circuit resizing to enable parasitic robust designs. A performance-driven placement with simultaneous fast incremental global routing is proposed to achieve accurate parasitic estimation. Device tuning is utilized during layout to compensate for layout induced performance degradations. This methodology allows sophisticated macromodels of performances versus device variables and parasitics to be used during layout synthesis to make it truly performance-driven. Experimental results of a 4GHz LNA and a mixer demonstrate fast parasitic closure with this methodology.

The introduction of simulation-based analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 103 to 105 fully simulated circuit solution candidates. What might we do with all this circuit data? We show how to adapt recent ideas from large-scale data mining to build models that capture significant regions of this visited performance space, parameterized by variables manipulated by synthesis, trained by the data points visited during synthesis. Experimental results show that we can automatically build useful nonlinear regression models for large analog design spaces.

This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufacturing process. To manage complexity and time-to-market, SoC designs require a high level of automation and reuse. Digital methodologies are inapplicable to analog IP, which relies on tight control of low-level device and circuit properties that vary widely across manufacturing processes. This analog synthesis solution automates these tedious, technology specific aspects of analog design. Unlike previously proposed approaches, ASF extends the prevalent "schematic and SPICE" methodology used to design analog and mixed-signal circuits. ASF is topology and technology independent and can be easily integrated into a commercial schematic capture design environment. Furthermore, ASF employs a novel numerical optimization formulation that incorporates classical downhill techniques into stochastic search. ASF consistently produces results comparable to expert manual design with 10/spl times/ fewer candidate solution evaluations than previously published approaches that rely on traditional stochastic optimization methods.

Article Share on Low-power technology mapping for mixed-swing logic Authors: Rob A. Rutenbar Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PAView Profile , L. Richard Carley Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PAView Profile , Roberto Zafalon STMicroelectronics, Agrate (MI), Italy STMicroelectronics, Agrate (MI), ItalyView Profile , Nicola Dragone Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA and PDF Solutions, Desenzano (BS), Italy Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA and PDF Solutions, Desenzano (BS), ItalyView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 291–294https://doi.org/10.1145/383082.383171Online:06 August 2001Publication History 2citation209DownloadsMetricsTotal Citations2Total Downloads209Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

A persistent criticism of analog synthesis techniques is that they cannot cope with the complexity of realistic industrial designs, especially system-level designs. We show how recent advances in simulation-based synthesis can be augmented, via appropriate macromodeling, to attack complex analog blocks. To support this claim, we resynthesize from scratch, in several different styles, a complex equalizer/filter block from the frontend of a commercial ADSL CODEC, and verify by full simulation that it matches its original design specifications. As a result, we argue that synthesis has significant potential in both custom and analog IP reuse scenarios.

In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process induced delay variations so as to minimize energy dissipation while always guaranteeing the target operatingfrequency. For this purpose the delay of a critical path replica of the circuit being regulated is constantly compared with the target delay provide the regulator with the information needed to select the optimum voltage levels. The proposed solution is even more attractive in that no external components are required. Based on this scheme, a completely on-chip voltage regulator has been fabricated in a commercial 0.5μm CMOS process and used to generate the inner rail voltages for a DSP multiplier-accumulator (MAC) implemented in mixed swing QuadRail. Measured results indicate that the voltages generated by the regulator offer a very high degree of load regulation thus verifying the fast response time of the on-chip output buffer.

In this paper we present an approach to teaching an introductory course in electrical and computer engineering to freshmen engineering students. The primary distinguishing characteristics of our approach include: providing information in an experiential context or "teaching-in-context"; focusing on "black-box"-based hierarchical decomposition as an approach to understanding complex systems; and using piecewise linear models for nonlinear elements as a way to develop intuition and understanding about the workings of circuits. The experiential context is provided by having students carry out a series of laboratory exercises involving an exciting real-world electronic system. To date, we have developed laboratory exercises around a programmable robot and a Global Positioning System receiver. The greatest challenges in teaching an intellectually substantive course to entering freshmen are their lack, on average, of the mathematics and physics background that is taken for granted in most electrical and computer engineering courses. In this paper we demonstrate that by appropriate choice of material and presentation methods this challenge can be overcome.

We describe a synthesis system that takes operating range constraints and inter and intracircuit parametric manufacturing variations into account while designing a sized and biased analog circuit. Previous approaches to computer-aided design for analog circuit synthesis have concentrated on nominal analog circuit design, and subsequent optimization of these circuits for statistical fluctuations and operating point ranges. Our approach simultaneously synthesizes and optimizes for operating and manufacturing variations by mapping the circuit design problem into an infinite programming problem and solving it using an annealing within annealing formulation. We present circuits designed by this integrated synthesis system, and show that they indeed meet their operating range and parametric manufacturing constraints. And finally, we show that our consideration of variations during the initial optimization-based circuit synthesis leads to better starting points for post-synthesis yield optimization than a classical nominal synthesis approach.

Analog synthesis tools have traditionally traded quality for speed, substituting simplified circuit evaluation methods for full simulation in order to accelerate the numerical search for solution candidates. As a result, these tools have failed to migrate into mainstream use primarily because of difficulties in reconciling the simplified models required for synthesis with the industrial-strength simulation environments required for validation. We argue that for synthesis to be practical, it is essential to synthesize a circuit using the same simulation environment created to validate the circuit. In this paper, we develop a new numerical search algorithm efficient enough to allow full circuit simulation of each circuit candidate, and robust enough to find good solutions for difficult circuits. The method combines the population-of-solutions ideas from evolutionary algorithms with a novel variant of pattern search, and supports transparent network parallelism. Comparison of several synthesized cell-level circuits against manual industrial designs demonstrates the utility of the approach.

Analog synthesis tools have failed to migrate into mainstream use primarily because of difficulties in reconciling the simplified models required for synthesis with the industrial-strength simulation environments required for validation. MAELSTROM is a new approach that synthesizes a circuit using the same simulation environment created to validate the circuit. We introduce a novel genetic/annealing optimizer, and leverage network parallelism to achieve efficient simulator-in-the-loop analog synthesis.

At high linear recording densities, signal-dependent, correlated noise, due to the medium and correlated noise resulting from equalization, significantly degrades the error-rate performance of the Viterbi algorithm (VA). Longer length partial-response targets can alleviate this problem, however, only by increasing the state complexity of the VA. Two options for dealing with this problem are examined in this paper. The first option is class IV equalization followed by a VA that employs a modified branch metric specifically designed for correlated noise. This results in a substantially higher complexity VA. The other option involves adaptively locating an equalization target that limits noise correlation prior to Viterbi detection by placing a monic constraint on the target. Using data collected from state-of-the-art magnetic recording components, it is shown that monic target equalization followed by the normal VA significantly outperforms class IV equalization followed by the modified branch metric VA of similar complexity as well as conventional PRML.

This paper describes a completely on-chip voltage regulation technique for locally generating an adaptive low voltage power supply rail from a given higher voltage power supply without requiring any external component.The on-chip regulator, based on delay servoing, primarily comprises of a critical path replica, charge pump and a high performance voltage buffer which is the most critical component of the design.Simulation results in OSl.trn CMOS process demonstrate that the buffer offers a low DC output impedance, a high degree of voltage regulation (output ripple of 12% of Vdd) and a superior line regulation (upto the maximum clock frequency of SOMHz) even under strongly varying load conditions.The regulator response for a typical worst case load exhibits a maximum voltage fluctuation of 4% of Vdd with a reasonably fast response time.

Various high-speed techniques have been developed for multipliers, but with the increasing popularity of mobile computing, a recent goal has been to minimize power dissipation. A popular delay-reduction technique applied to adder circuits is polarity inversion of bits. As this optimization reduces transistor count, it also has the potential for lowering power dissipation, and can be effectively applied to Wallace tree partial product reduction stages. We illustrate how this technique reduces power, interconnect capacitance, and chip area. Power reduction of up to 25 % is achieved. 1.1 Keywords Multiplier, low power, inverse polarity.

This paper describes a new mixed-swing topology for dual-rail domino logic that results in a simultaneous energy and delay reduction. HSPICE simulation results for a 1-bit full adder cell show a 24 % delay decrease and a 24 % energy reduction for the mixed-swing topology compared to standard dual-rail domino. Energy and delay trends with supply voltage scaling are also presented for the adder cell. An 8-bit by 8-bit multiplier design with mixedswing dual-rail domino adders is presented. Simulation results show this implementation to be 10 % faster with an 18 % energy savings. 1.

High-frequency circuits are notoriously difficult to lay out because of the tight coupling between device-level placement and wiring. Given that successful electrical performance requires careful control of the lowest-level geometric features-wire bends, precise length, planarity, etc., we suggest a new layout strategy for these circuits: early floorplanning at the device level. This paper develops a floorplanner for radio-frequency circuits based on a genetic algorithm (GA) that supports fully simultaneous placement and routing. The GA evolves slicing-style floorplans comprising devices and planned areas for wire meanders. Each floorplan candidate is fully routed with a gridless, detailed maze-router which can dynamically resize the floorplan as necessary. Experimental results demonstrate the ability of this approach to successfully optimize for wire planarity, realize multiple constraints on net lengths or phases, and achieve reasonable area in modest CPU times.

One of the major problems faced by the designer when operating CMOS static logic circuits at low power supply voltages (normalized to VT is that the delay spread introduced by today's IC manufacturing variations can increase dramatically. In this paper we describe an approach for decreasing the delay spread and power spread in ICs based on adaptively servoing the circuits between static CMOS operation and QuadRail operation. An on-chip series-regulator employing a dummy delay path is used to generate the adaptive low swing power supply rails making this approach fully compatible with a standard CMOS IC design methodology. Simulation results are presented demonstrating that for a 16*16+36-bit multiplier-accumulator designed in 0.5µm CMOS process the proposed approach decreases the delay spread from 3.9X to 2.3X and the power spread from 3.6X to 1.8X.

High-frequency circuits are notoriously difficult to lay out because of the tight coupling between device-level placement and wiring. Given that successful electrical performance requires careful control of the lowest-level geometric features—wire bends, precise length, proximity, planarity, etc.—we suggest a new layout strategy for these circuits: early floorplanning at the device level. This paper develops a floorplanner for RF circuits based on a genetic algorithm (GA) that supports fully simultaneous placement and routing. The GA evolves slicing-style floorplans comprising devices and planned areas for wire meanders. Each floorplan candidate is fully routed with a gridless, detailed maze-router which can dynamically resize the floorplan as necessary. Experimental results demonstrate the ability of this approach to successfully optimize for wire planarity, realize multiple constraints on net lengths or phases, and achieve reasonable area in modest CPU times.

This paper describes and explores the design space of a mixed voltage swing methodology for lowering the energy per switching operation of digital circuits in standard submicron complementary metal-oxide-semiconductor (CMOS) fabrication processes. Employing mixed voltage swings expands the degrees of freedom available in the power-delay optimization space of static CMOS circuits. In order to study this design space and evaluate the power-delay tradeoffs, analytical polynomial formulations for power and delay of mixed swing circuits are derived and HSPICE simulation results are presented to demonstrate their accuracy. Efficient voltage scaling and transistor sizing techniques based on our analytical formulations are proposed for optimizing energy/operation subject to target delay constraints; up to 2.2/spl times/ improvement in energy/operation is demonstrated for an ISCAS'85 benchmark circuit using these techniques. Experimental results from HSPICE simulations and measurements from an And-Or-Invert (AO1222) test chip fabricated in the Hewlett-Packard 0.5 /spl mu/m process are presented to demonstrate up to 2,92/spl times/ energy/operation savings for optimized mixed swing circuits compared to static CMOS.

Article Free Access Share on Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies Authors: L. Richard Carley Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PAView Profile , Georges G. E. Gielen Electrical Engineering, Katholieke Universiteit Leuven, Leuven, Belgium Electrical Engineering, Katholieke Universiteit Leuven, Leuven, BelgiumView Profile , Rob A. Rutenbar Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PAView Profile , Willy M. C. Sansen Electrical Engineering, Katholieke Universiteit Leuven, Leuven, Belgium Electrical Engineering, Katholieke Universiteit Leuven, Leuven, BelgiumView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 298–303https://doi.org/10.1145/240518.240573Online:01 June 1996Publication History 36citation523DownloadsMetricsTotal Citations36Total Downloads523Last 12 Months21Last 6 weeks5 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper explores the decrease in interconnect capacitance that can be achieved by the use of mesa-shaped wires. A methodology for creating mesa interconnect is described that uses simple postprocessing steps following standard CMOS IC foundry processes. By removing the oxide between metal lines and replacing it with air, the fringing capacitance between metal lines and the substrate is reduced as is the capacitance between adjacent metal lines. The decrease in capacitance resulting from the removal of the oxide between metal conductors is predicted using a 2-D electrostatic field solver and verified by measurements on test structures fabricated in an 0.5 /spl mu/m HP CMOS process. Capacitance of mesa interconnect structures was reduced by roughly 40% for these test structures. For circuits dominated by interconnect capacitance, cutting the parasitic capacitance by 40% cuts the power dissipation by 40% and cuts the gate delay by 40%. Therefore the power-delay product is reduced by roughly 65% and the energy-delay product is reduced by roughly 80%. Although many issues must still be addressed to make this form of interconnect practical, the results presented in this paper suggest that the rewards in terms of decreasing capacitance could well be worth investing the effort to solve these issues.

This paper describes and explores the design space of a four power-supply rail methodology (called Mixed Swing QuadRail) for performing low voltage logic in a high threshold voltage CMOS fabrication process. Power and delay trade-offs are studied to suggest approaches for efficient selection of voltage levels and buffer transistor sizes. Polynomial models for QuadRail power and delay are derived to show that at reduced I/O swings (sub-1 V), both under- and over-sizing of transistors can lead to steeply increased delays. Transistor sizing techniques are proposed for optimizing delay and energy per logic operation as a function of load capacitance and voltage levels. Experimental results from detailed HSPICE simulations and an And-Or-Invert (AOI222) QuadRail test chip fabricated in the Hewlett-Packard 0.5 /spl mu/m process are presented to support the models and demonstrate significant power reduction compared to static CMOS.

We present a new synthesis strategy that can automate fully the path from an analog circuit topology and performance specifications to a sized circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel unconstrained optimization formulation of the circuit synthesis problem. We have implemented this strategy in a pair of tools called ASTRX and OBLX. To show the generality of our new approach, we have used this system to resynthesize essentially all the analog synthesis benchmarks published in the past decade; ASTRX/OBLX has resynthesized circuits in an afternoon that, for some prior approaches, had required months. To show the viability of the approach on difficult circuits, we have resynthesized a recently published (and patented), high-performance operational amplifier; ASTRX/OBLX achieved performance comparable to the expert manual design. And finally, to test the limits of the approach on industrial-sized problems, we have synthesized the component cells of a pipelined A/D converter; ASTRX/OBLX successfully generated cells 2-3/spl times/ more complex than those published previously.

Proposed in this paper are two key components for a magnetic recording channel detection system: a continuous-time current-mode forward equalizer and a sample-and-hold current-mode backward equalizer. Both are designed for use with the Fixed Delay Tree Search with Decision Feedback (FDTS/DF) detection algorithm. The forward equalizer architecture consists of a bank of bandpass and allpass filters. The backward equalizer uses current steering principles to implement a high-speed robust architecture. Simulations show that an FDTS system utilizing the proposed forward equalizer architecture has performance equivalent to that of a system including an FIR equalizer with 24 taps. A transresistance integrator and transconductance amplifier are used to realize a current-mode, variable-gain integrator building block. This building block is used to implement the tunable bandpass and allpass filters in the equalizer. Simulations based on a 0.8 /spl mu/m CMOS process show that the forward equalizer is tunable up to 82 MHz. For a given FDTS/DF detection scheme utilizing 2/3(1,7) coding, this translates into approximately 130 to 164 Msamples/s. The corresponding power dissipation is 86 mW from a 3 V power supply. Simulation of the backward equalizer indicates a maximum operating-speed of approximately 100 Msamples/s.

A new approach to cell-level analog circuit synthesis is presented. This approach formulates analog synthesis as a Mixed-Integer Nonlinear Programming (MINLP) problem in order to allow simultaneous topology and parameter selection. Topology choices are represented as binary integer variables and design parameters (e.g., device sizes and bias voltages) as continuous variables. Examples using a Branch and Bound method to efficiently solve the MINLP problem for CMOS two-stage op amps are given.>

We describe ASTRX/OBLX, a synthesis system that can size high-performance analog circuit topologies to meet usersupplied linear performance specifications without designer-supplied equations.We present synthesis results for a large suite of circuit benchmarks and show that, when compared to prior approaches, ASTRX/OBLX can synthesize high-performance circuits with up to 3 orders of magnitude less initial design effort.

We describe a synthesis system that takes operating range constraints and inter- and intra-circuit parametric manufacturing variations into account while designing a sized and biased analog circuit. Previous approaches to CAD for analog circuit synthesis have concentrated on nominal analog circuit design, and subsequent optimization of these circuits for statistical fluctuations and operating point ranges. Our approach simultaneously synthesizes and optimizes for operating and manufacturing variations by mapping the circuit design problem into an Infinite Programming problem and solving it using an annealing within annealing formulation. We present circuits designed by this integrated synthesis system, and show that they indeed meet their operating range and parametric manufacturing constraints.

This paper addresses the data detection problem of intersymbol interference (ISI) channels with a specific modulation code-constraint known as the (d, k) run-length-limited (RLL) constraint, a popular modulation code-constraint for data storage channels as well as certain communication channels. A computationally efficient sequence detection algorithm is proposed which yields a performance close to that of the maximum likelihood sequence detector when applied to such ISI channels. The proposed detector is derived as a high signal-to-noise ratio approximation to the delay-constrained optimum detector, one which minimizes the symbol error probability given a fixed decision-delay constraint. The proposed algorithm is essentially a fixed-delay tree search (FDTS) algorithm with systematic ambiguity checking and is closely related to existing finite-depth tree search algorithms. It is observed that long critical error events common in uncoded ISI channels are eliminated by the RLL constraint. Based on this observation, we show that for some important RLL constrained channels, the proposed FDTS algorithm yields the same minimum Euclidean distance between distinguishable channel output sequences as the unconstrained maximum likelihood sequence detector.>

This paper presents new results in constraint-directed placement and routing of device-level analog cells. We describe the first algorithm for latchup-aware device placement that guarantees sufficient placement of well/substrate contacts by simultaneous placement of latchup protection geometry and devices. A novel cost-to-target predictor for cost-based A/sup */ routing, and a new scheme for pruning evolving paths that violate user-supplied constrained routing of analog signals in dense placements are described. Experimental results suggest the strategy avoids the artifacts of length-for-crosstalk trade-offs seen in earlier algorithms, and allows users more fine-grain control of the routing of defense, high-performance cells. An implementation of these ideas in the tool set KA III is used to derive improved layouts from several analog cells.

Techniques for global and detailed routing of the macrocell-style analog core of a mixed-signal ASIC are discussed. A comparatively simple geometric model of the problem is combined with an aggressive simulated annealing formulation that selects paths while accommodating numerous signal-integrity constraints. Experimental results demonstrate that it is critical to attack such constraints both globally (system-level) and locally (channel-level) to meet designer-specified performance targets.>

The authors describe novel techniques for simultaneous device placement and detailed routing of analog cells. Both nets and devices are treated as placeable, malleable objects in a common simulated-annealing framework. A detailed routing abstraction called a k-bend net limits the complexity of each net's topology, and allows simple incremental net reshaping during annealing. Analog layouts in which the critical interacting nets are simultaneously embedded during device placement prove to be superior, in terms of performance-limiting crosstalk violations, to sequentially placed and routed layouts.>

A CAD (computer-aided design) tool that accurately sizes analog circuits in short-channel CMOS processes using SPICE-quality device models and constrained optimization techniques is presented. All knowledge about device behavior is embedded within an encapsulated device evaluator which simplifies the description of the analog circuit that must be provided by an expert designer, and makes that description independent of the specific device type and technology. The use of constrained optimization allows the KCL and KVL constraints that determine the DC operating point of a circuit to be formulated and solved simultaneously with the performance constraints. In addition, the constrained optimization formulation of the analog design problem makes it easy for the user to study tradeoffs in the circuit design space by varying the performance constraints. Simulation results demonstrate the tool's ability to accurately synthesize high-performance two-stage CMOS op amps in 2 mu m and 1.2 mu m CMOS processes.>

The authors present a very fast lightstripe rangefinder based on an IC array of photoreceptor and analog signal processor cells which acquires 1000 frames of range image per second-two orders of magnitude faster than currently available rangefinding methods. Unlike a conventional lightstripe range-finder, which obtains a frame of range image by the step-and-repeat process of projecting a stripe and grabbing and analyzing a camera image, the VLSI sensor array of this rangefinder gathers range data in parallel as a scene is swept continuously by a moving stripe. Each cell continuously monitors the output of its photoreceptor, and detects and remembers the time at which it observed the peak incident light intensity during the sweep of the stripe. Prototype rangefinding systems have been built using a 28*32 array of these sensing elements.>

A hierarchically structured framework for analog circuit synthesis is described. This hierarchical structure has two important features: it decomposes the design task into a sequence of smaller tasks with uniform structure, and it simplifies the reuse of design knowledge. Mechanisms are described that select from among alternate design styles and translate performance specifications from one level in the hierarchy to the next lower, more concrete level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers from performance specifications and process parameters. Measurements from detailed circuit simulation and from actual fabricated analog ICs based on OASYS-synthesized designs demonstrate that OASYS is capable of synthesizing functional circuits.>

ANAGRAM models cell layout in the style of a macrocell place-and-route problem. Individual cell primitives (transistor-level objects of widely varying sizes) are the macrocells. Module generation techniques are used to generate these internal primitives and to preserve critical matching and symmetries. An annealing-based placement algorithm then places these primitives. This is followed by a novel line-expansion signal router, which includes mechanisms to avoid noise coupling due to internodal capacitances between the signal wires and shared parasitic resistances in the DC supply wiring and operates in an iterative improvement fashion to eliminate such violations. Layouts for several custom CMOS cells have been successfully generated. Circuit-simulation results based on cell extractions demonstrate the effectiveness of the crosstalk-avoidance mechanisms.>

Mechanisms needed to meet stringent performance demands in a hierarchically structured analog circuit synthesis tool are described. Experiences with adding a high-speed comparator design style to the OASYS synthesis tool are discussed. It is argued that design iteration (the process of making a heuristic design choice, following it through to possible failure, then diagnosing the failure and modifying the overall plan of attack for the synthesis) is essential to meet such performance demands. Examples of high-speed comparators automatically synthesized by OASYS are presented. Designs competitive in quality with manual expert designs, e.g. with response time of 6 ns and input drive of 1 mV, can be synthesized in under 5 seconds on a workstation.>

A high-level synthesis tool, CLANS, that accepts data converter performance specifications and selects optimal block-level component specifications for noise-shaping coders is presented. CLANS both predicts the performance of multibit noise-shaping coders (both A/D and D/A converters) and determines optimal loop-filter transfer functions. The performance of CLANS' designs has been verified using both block-level simulation and experimental measurements on a CMOS prototype D/A converter.>

Built-in current (BIC) testing involves the monitoring of power bus currents in a VLSI circuit, as a means of detecting processing defects in the circuit. The design and performance of a prototype BIC sensor for static CMOS are discussed. It has been demonstrated that a fully-operational BIC sensor can be designed using a standard CMOS process. The presented design met all basic requirements: it was small, it caused only a small degradation of the performance of the monitored module, and it provided sufficient current resolution. The main disadvantage of the described design, however, was a substrate current caused by the structure of the bipolar transistor.>

Experimental results obtained with OASYS, a behavior-to-structure synthesis tool for analog circuits, are described. In particular, measurements from fabricated analog ICs based on OASYS-synthesized designs are presented, and used to verify that OASYS is capable of producing real, functional circuits. Possibilities for automatically exploring the space of designable analog circuits, an ability made possible by a fast, automatic synthesis tool such as OASYS, are also described. Examples of using OASYS to explore tradeoffs among process and performance specifications are presented.>

An organization for a knowledge-based analog circuit synthesis tool is described. Analog circuit topologies are represented as a hierarchy of functional blocks; a planning mechanism is introduced to translate performance specifications between levels in this circuit hierarchy. A prototype implementation, OASYS, synthesizes sized transistor schematics for simple CMOS operational amplifiers from performance specifications and process parameters, and demonstrates the workability of the approach.