Despite the fact that more and more electronic design is comprised of analog and mixed signal content, the design flows and methodologies in this area are lagging behind the pace of innovation in digital design. For sure, analog designers are in shorter supply, but this only makes the need for improvements and efficiency that much greater. Only of late have we seen production-worth attempts at functions such as analog synthesis and optimization reach the market. What is needed in today's analog design flow? What are the key technologies that are missing? How does the existing “food chain” need to work together to drive greater efficiencies?

This paper presents an efficient dc MOSFET model for accurate simulation of analog circuits. A new approach to model channel length modulation is presented. An empirical expression for channel length modulation is derived from measurements. This is used to model the observed behavior of g/sub D/ with gate, drain, and substrate bias. Some of the models commonly used for circuit simulation do not predict the effects of gate and substrate bias adequately. A new smoothing function is used to unify the linear and saturation regions in a single expression. Continuity of transconductance is maintained between the weak and strong inversion regions. Model efficiency is maintained by avoiding the use of transcendental functions in the smoothing techniques. We demonstrate>

: Currents flowing in the power and ground (P&G) lines of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Maximum current estimates are therefore needed in the P&G lines to determine the severity of the voltage drop problems and to properly design the supply lines to eliminate these problems. These currents, however, depend on the specific input patterns that are applied to the circuit. Since it is prohibitively expensive to enumerate all possible inputs, this problem has, for a long time, remained largely unsolved. In [1], we proposed a pattern-independent, linear time algorithm (iMax) that estimates an upper bound envelope of all possible current waveforms that result from the application of different input patterns to the circuit. While the bound produced by iMax is fairly tight on many circuits, there can be a significant loss in accuracy due to correlations between signals internal to the circuit. In this paper, we present ...

One of the most important factors in achieving an accurate and efficient device simulation today is a good grid. However, an effective grid error indicator for the device simulation has been lacking; thus, it is very difficult to know how accurate the simulation results are. Previous papers have suggested that the local truncation error (LTE) is not a good indicator for grid discretization error. In this paper we show that the dominant factor in the LTE derivation has been ignored. With the correct formulation it is shown that LTE is a major source of the solution error. Since LTE is easy to calculate, our methodology provides up to orders of magnitudes savings in CPU time compared to other algorithms. This adaptive regridding on LTE provides overall simulation speedups of 10X for medium-sized examples. With little overhead, the LTE is extended to be an effective error indicator for device terminal characteristics, such as drive current and threshold voltage, which can only be obtained previously with large effort.

Selected integrated circuit (IC) reliability issues are discussed within the context of the design-in reliability concept. The electrical reliability issues discussed are latchup, electrostatic discharge, hot carrier effects, thin dielectric breakdown, and electromigration. Examples of the environmental reliability issues discussed are alpha -particle induced soft errors, thermal stress, mechanical stress, and corrosion.>

An intelligent partial Gauss-Seidel scheme (PGS) for general circuit simulation is described. This approach is a novel combination of direct solution using incomplete LU factorization, and iterative solution using Gauss-Seidel relaxation. The method converges faster and more reliably than Gauss-Seidel, while taking a comparable amount of execution time per iteration. Reliable analytic rules are derived such that terms that would be relaxed in Gauss-Seidel are relaxed only if they are considered small by applying these rules. Solution speeds up to ten times faster than direct methods have been demonstrated and higher gains are anticipated for larger circuits. This scheme is robust and accurate for circuits with many different element types, including bipolar transistors, MOSFETs, diodes, inductors, and dependent sources.>

Algorithms for transient mixed-level circuit and device simulation using a full two-carrier three-dimensional (3-D) device simulator SIERRA and the circuit simulator SPICE3 are presented. Circuit and device simulator coupling algorithms that are suited for two-dimensional mixed-level circuit and device simulation using direct solvers cannot be successfully employed when iterative solution techniques are used in 3-D device simulation. New algorithms to couple the circuit and 3-D device simulator have been developed and evaluated. The importance of 3-D mixed-level circuit and device simulation is demonstrated by applying it to single-event upset in CMOS SRAM cells.>

The authors investigate a power estimation technique for VLSI that combines the accuracy of simulation-based techniques with the speed of the probabilistic techniques. The resulting method is statistical in nature; it consists of applying randomly generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. The authors present the algorithm and experimental results, and discuss the superiority of the approach.>

An alternative technique for power estimation that combines the accuracy of simulation-based techniques with the speed of the probabilistic technique is investigated. The resulting method is statistical in nature; it consists of applying randomly-generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. The algorithm and experimental results are presented and the superiority of this approach is discussed.>

The authors describe algorithms for transient mixed-level circuit and device simulation using a two-carrier three-dimensional device simulator SIERRA and the circuit simulator SPICE3. It is pointed out that algorithms well suited to 2D mixed-level circuit and device simulation cannot be successfully used. The memory and CPU time requirements in 3D device simulation necessitate it the use of iterative solution techniques at the device level, which impose an additional constraint in developing efficient algorithms. Two node tearing schemes are shown to be the most promising schemes for coupling the circuit and device simulators. An application of 3D mixed-level simulation to the study of single-event upset of SRAM cells is presented.>

The improvement in computational throughput of VLSI circuit simulation is addressed. A high degree of natural parallelism exists in the circuit simulation problem; potentially a large number of processor can be used efficiently. Three distinct approaches for obtaining parallel execution in direct-method circuit simulators are investigated. These approaches differ primarily in the size of the individual tasks used to obtain parallel execution. The relative advantages of each approach are examined, and performance data from simulations on parallel processing systems are presented. For the third approach, very good parallel efficiency was obtained; in some cases, 99% parallelism has been observed.>

The probabilistic simulation approach is extended to include the computation of the variance waveform of the power/ground current, in addition to its expected waveform. The focus is on the problem of estimating the median time-to-failure (MTF) due to electromigration (EM) in the power and ground buses of CMOS circuits. Theoretical results that quantify the relationship between the MTF and the statistics of the stochastic current are presented. This leads to a more accurate estimate of the MTF that requires both the expected and variance waveforms. A novel technique is then presented to compute the variance waveform for CMOS circuits, which has been incorporated into the probabilistic simulator CREST. Results of this implementation demonstrating efficiency and accuracy on a number of circuits are provided. The authors use these results to study the importance of the variance waveform by estimating its contribution to the MTF relative to that of the expected waveform.>

The authors present a general purpose, parallel matrix solver based on the conjugate gradient squared (CGS) method which features a novel preconditioning scheme commensurate with massive parallel computing. The solver algorithm has been successfully used for solving linear systems of equations arising from circuit and device simulations with MOS and bipolar junction transistor (BJT) circuits, both digital and analog, as well as high-level injection conditions in devices. The performance of the algorithm can be further improved by a matrix partitioning scheme.>

A current-estimation approach to support the analysis of electromigration (EM) failures in power supply and ground buses of CMOS VLSI circuits is discussed. It uses the original concept of probabilistic simulation to efficiently generate accurate estimates of the expected current waveform required for electromigration analysis. Thus, the approach is pattern-independent and relieves the designer of the tedious task of specifying logical input waveforms. This approach has been implemented in the program CREST (current estimator) which has shown excellent accuracy and dramatic speedups compared with traditional approaches. The approach and its implementation are described, and the results of numerous CREST runs on real circuits are presented.>

Two techniques for general circuit simulation, an intelligent, partial Gauss-Seidel scheme (PGS) and a preconditioned conjugate-gradient scheme (PLUCGS), are described. Both techniques are robust and accurate for bipolar and MOS analog and digital circuits. PGS is a novel combination of direct solution, using LU factorization, and iterative solution, using Gauss-Seidel relaxation. The method converges faster and more reliably than Gauss-Seidel, while taking a comparable amount of execution time per iteration. Solution speeds up to 6 times faster than direct methods have been demonstrated and higher grains are anticipated for larger circuits. The second method, PLUCGS, uses a partial LU factorization as a preconditioner; a vectorized implementation on a CONVEX C-240 computer is 5-7 times faster than the direct solution method with only one-fourth the memory requirements.>

A novel technique for deriving the variance waveform for CMOS circuits is presented. Using this technique, the authors establish the importance of the variance waveform by showing that its contribution to the mean-time-to-failure estimate can be in the range of 100% to 200% relative to that of the expected waveform. The technique has been built into the probabilistic simulator CREST and has shown good agreement with SPICE, as well as excellent speedup.>

The estimation of the median time-to-failure (MTF) due to electromigration in the power and ground buses of VLSI circuits is addressed. In their previous work (Proc. 25th ACM/IEEE Design Autom. Conf., p.294-9, 1988), the authors presented a novel technique for MTF estimation based on a stochastic current waveform model. They derived the mean (or expected) waveform (not a time average) of such a current model and conjectured that it is the appropriate current waveform to be used for MTF estimation. The authors prove that conjecture and present new theoretical results which show the exact relationship between the MTF and the statistics of the stochastic current. This leads to a more accurate technique for deriving the MTF which requires the variance waveform of the current, in addition to its mean waveform. The authors then show how the variances of the bus branch currents can be derived from those of the gate currents, and describe several simplifying approximations that can be used to maintain efficiency and, therefore, make possible the analysis of VLSI circuits.>

SIERRA is a 3-D general-purpose semiconductor-device simulation program which serves as a foundation for investigating integrated-circuit (IC) device and reliability issues. This program solves the Poisson and continuity equations in silicon under DC, transient, and small-signal conditions. Executing on a vector/parallel minisupercomputer, SIERRA utilizes a matrix solver which uses an incomplete LU (ILU) preconditioned conjugate gradient square (CGS, BCG) method. The ILU-CGS method provides a good compromise between memory size and convergence rate. The authors have observed a 5* to 7* speedup over standard direct methods in simulations of transient problems containing highly coupled Poisson and continuity equations such as those found in reliability-oriented simulations. The application of SIERRA to parasitic CMOS latchup and DRAM (dynamic random-access memory) single-event-upset studies is described.>

To exploit time-domain latency in circuit simulation using direct methods, an accurate, computationally efficient model for slowly moving, dormant portions of the circuit is required. A new, implicit integration method, the overdetermined polynomial method (ODPM), has been developed which permits the formulation of an accurate latent model. Using the ODPM integration method, the Jacobian of a dormant subcircuit need not be reevaluated over a large number of time steps of varying size. An accurate Norton equivalent circuit that emulates the impedance and current characteristics of the subcircuit can be obtained without reevaluation of the Jacobian or nonlinear charge computations. This new approach for utilizing latency produces significant improvements in circuit simulation speed with no decrease in accuracy or generality. The authors have demonstrated speed gains of 3 to 20 times over TISPICE for several large circuits.>

An efficient MOSFET model for accurate prediction of the drain current and the drain conductance of a short-channel MOSFET is presented. Earlier models for channel length modulation are not suitable for simulating analog circuits for which the drain conductance is important. Empirical expressions derived from measured I-V characteristics are used to fit well the behavior of drain conductance with gate and substrate bias predicted by the model, which thus overcomes the limitations of earlier models. The model was implemented in SPICE, and several simple circuits have been tested without encountering any convergence problems.>

An approach for modeling dormant subcircuits is presented that utilizes iteration latency to provide speed improvements that are comparable to the potential speed improvements of an independent time step approach. This scheme minimizes the work required on the first iteration at a time point, which is the normal limiting factor in iteration latency schemes. However, since simulations are performed for each subcircuit at each time point, the penalty for backing up when truncation error is unacceptable is minimized.>

CREST is a pattern-independent current estimation approach developed to support electromigration analysis tools. It uses the powerful, original concept of probabilistic simulation to generate accurate estimates of the expected current waveforms efficiently. The original implementation of CREST is extended to circuits containing pass transistors, reconvergent fanout, and feedback, and heuristics to simulate circuits with large reconvergent fanout or feedback blocks efficiently are provided. The results of using CREST on several real circuits are presented.>

Two techniques are presented for optimizing the parametric yield of digital MOS circuit blocks for VLSI designs. The first is based on quasi-Newton methods and utilizes the gradient of the yield. A novel technique for computing this yield gradient is derived and algorithms for its implementation are discussed. Geometrical considerations motivate the second method which formulates the problem in terms of a minimax problem. Both yield optimization techniques utilize transient sensitivity information from circuit simulations. Encouraging results have been obtained thus far; several circuit examples are included to demonstrate these techniques.>

A system of CAD programs, called SPIDER, for ensuring adequate current-carrying capacity in VLSI circuits has been developed. The approach is hierarchical, and it automates and simplifies many of the tasks previously performed by the circuit designer. The system converts transient current waveforms into dc electromigration equivalent values, and includes an algorithm for determining the line width adjustments necessary for meeting specified median-time-to-failure (MTF) requirements. SPIDER also computes voltage drops with respect to a reference node and calls upon an optimization algorithm for correcting violations of a voltage drop specification.

An analytical predictor/CAD model for a short-channel buried-channel MOSFET is reported. The proposed model can be used to predict the anomalous threshold voltage shift associated with the short-channel buried-channel MOSFET. The characteristic is shown to be caused by the shifting of the operational mode from the surface to the buried channel. Current equations which are applicable to the short-channel buried-channel device are derived. For the purpose of circuit simulations, a computationally efficient CAD current model is also developed. The current characteristics calculated from the model equation are found to be in good agreement with experimental results. By using the CAD current equations, a charge model for the intrinsic buried-channel device is formulated. The charge model equations can be used to model the intrinsic capacitances for SPICE simulations.

An integrated and efficient approach is developed for automated statistical circuit design. One major problem in statistical circuit design for MOS VLSI is the prohibitively expensive computational requirements. The objective is to find realistic, accurate, and efficient solutions for use in the MOS VLSI design area. An automated statistical characterization system has been developed to characterize a large number of MOS devices to obtain statistical information on device parameters. A statistical model for MOS VLSI circuits has been developed in which only the interdie variations are considered, since they are much larger than the local intradie variations. Therefore, the set of statistical variables are different from the set of design parameters, and this leads to a resolution of the problem of dimensionality associated with statistical design. In this statistical model, variations in device length and width, oxide capacitance, and flat band voltage, have been shown to be the principal process factors responsible for the statistical variation of device characteristics. A scalable MOS model has been developed to represent changes in the device model parameters as functions of these principal factors. This accurate and simple statistical modeling approach uses only four statistical variables, and thus permits computationally efficient statistical parametric yield estimation (SPYE). The direct approach for transient sensitivity computation has been implemented in SPICE to allow very efficient computation of performance function sensitivities. An efficient technique for computing the yield gradient using the SPYE and transient sensitivity results is discussed and an example is presented to demonstrate its use in parametric yield optimization.

This paper discusses the algorithms and implementation necessary for computing time domain sensitivities during circuit simulation. The adjoint approach and the direct approach have been studied, and it was concluded that the direct approach is the best for implementation. The direct approach allows the transient sensitivities to be computed concurrently in time with the normal simulation, and it has been demonstrated that accurate sensitivity computations can be obtained, by simply allowing the sensitivity circuits to use the same time steps as the original circuit. This implementation also incorporates the charge based model for the MOSFET's and those sensitivity derivations are shown. It has been found that the responses of the sensitivity circuits can be discontinuous, and that this is due to discontinuities in the derivatives of the charge with respect to voltage. Derivations for various performance function sensitivities in terms of the response sensitivities are also given.

VLSI circuit simulation requires computationally efficient MOSFET models. In this paper, VLSI circuit simulator models for the active device and some important passive devices are described. A quasi-physical short channel MOSFET current model is derived. This current model contains both above-threshold and subthreshold components. The values of the model parameter are extracted automatically from measured I-V data. The reduction in process information in this representation is shown to be tolerable using a proper quantization of the geometry and device type space. Narrow width effect is also included. A charge conserving MOSFET capacitor model is also given. The importance of the parasitic devices on VLSI circuit is shown and a model for the fringing capacitance due to finite gate thickness is introduced. A "process box" based on the statistical variation of parameters is extracted from a completely automated device characterization system. Experimental results indicate that the width and length are independent random variables. This statistical information allows the circuit response to be simulated across the process window.