Demo Data from EDBT 2026 / reviewers in the wild / expert
Darren Galpin
dblp:86/2743
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2002
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 2002 | A comparison of three verification techniques: directed testing, pseudo-random testing and property checking · DAC 2002 |
Electronic design automation › hardware verification and test › hardware verification
property checking |
0.0 | 1 | 2002 | A comparison of three verification techniques: directed testing, pseudo-random testing and property checking · DAC 2002 |
Electronic design automation › hardware verification and test › random testing
pseudorandom testing |
0.0 | 1 | 2002 | A comparison of three verification techniques: directed testing, pseudo-random testing and property checking · DAC 2002 |
Methods — techniques the papers use, named apart from their topics
specman · 0.0gateprop · 0.0VHDL bus functional models · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2002 | A comparison of three verification techniques: directed testing, pseudo-random testing and property checkingabstractThis paper describes the verification of two versions of a bridge between two on-chip buses. The verification was performed just as the Infineon Technologies Design Centre in Bristol was introducing pseudo-random testing (using Specman) and property checking (using GateProp) into their verification flows and thus provides a good opportunity to compare these two techniques with the existing strategy of directed testing using VHDL bus functional models. Mike Bartley, Darren Galpin, Tim Blackmore |
DAC | 2 |