Open-loop floating inverter amplifier (FIA) is widely used in noise shaping filter in SAR ADCs. However, its gain suffers from PVT variation, which primarily affects the shaping factor. Traditional trimming method adjust its gain by increasing or decreasing the effective reservoir capacitor. While adding additional I/O and cumbersome testing, the mere adjustment of reservoir capacitor also faces numerous limitations. This work presents a onetime self-calibrated scheme for FIA in noise shaping SAR ADCs, with neglectable dynamic power. Implementation of calibration adopt a coarse auxiliary cDAC, with most of remaining circuit reusing in main SAR ADC, indicating the cost advantage our design. Simulation results shows that for a 16× designed gain, the original gain fluctuated from 9.8× to 19×. Proposed calibration performed well at stabilizing gain at 16±0.5× under most of PVT corners. The scheme could refer to any other N× gain as well.

This paper presents a low phase noise (PN) and low power voltage-controlled oscillator (VCO) for Sub-7 GHz applications. We introduce a novel Colpitts VCO with forward body bias technique designed to augment the negative transcon-ductance and to optimize PN. The integration of orthogonal-coupled VCO core is employed for a wide frequency tuning range (FTR) based on the previous frequency expansion developed by the dual-mode, with capacitor banks and varactors. Moreover, a switched varactor unit is employed to realize KVCO linearization and optimize the frequency regulation range. Designed in 65-nm CMOS, the measured results exhibit a low PN of -139.8 dBc/Hz at 10 MHz offset and a figure-of-merit (FOM) of 191.1 dBc/Hz from a 6.108 GHz carrier, while the FTR is 50.6% from 9.13 to 15.31 GHz. The proposed VCO consumes 2.78mW at 0.72-V supply voltage.

This paper presents a fast transient flipped-voltage-follower-based low-dropout regulator (FVF LDO) with improved gate buffer and level-triggered transient enhancement circuit (LTTEC) in a 22 nm process. The fast loop composed of an FVF and the improved gate buffer exhibits ultra-high bandwidth and high slew rate. The proposed LTTEC can supply additional sourcing or sinking current to reduce the undershoot or overshoot during load transitions. The introduced bulk driven technique can effectively improve the power supply rejection (PSR) performance. The proposed LDO achieves 0.25ns response time with simulated 40.0 mV undershoot voltage and 36.7 mV overshoot voltage for the load current transition between 100 µA and 20 mA within 0.1 ns.

In a network processor, multiple processor cores share a centralized memory, whose latency and bandwidth easily become bottlenecks. Unlike CPUs or GPUs, network processors serve for packets and do not execute programs in units of tasks or processes. Therefore, a dedicated scheduling policy of centralized memory must be designed for packets. In this paper, we propose an efficient memory access scheduling policy when a great number of packets access centralized memory. Compared with traditional scheduling strategies such as synchronous RR and synchronous DRR, it performs dynamic scheduling based on real-time situations of packets and calculates the scheduling result through the packet status matrix. As a result, it can reduce the average memory access latency by 29.44%, thereby increasing the packet bandwidth of the network processor system by 5.74%.

This paper presents a continuous-time (CT) Sturdy multistage noise-shaping (SMASH) Delta-sigma Modulator (DSM), proposing a quantization noise extraction scheme without traditional analog delay matching circuits, improving modulator’s robustness and relaxing performance requirement for building blocks. For power-efficiency, the first-stage’s quantizer is designed with a 5-bit Voltage Controlled Oscillator (VCO) based analog-to-digital converter (ADC) and the second-stage’s quantizer is implemented by a 5-bit first-order noise-shaping (NS) successive approximation register (SAR) ADC. A transistor-level prototype is implemented in 40nm CMOS and the simulation results show that the modulator’s SFDR and SNDR is 85.8dB and 70.4dB respectively over a bandwidth (BW) of 20MHz while consuming 7.13mW, leading to an excellent FoM of 164.9dB.

A 14-bit 6.0-GS/s current-steering digital-to-analog converter (DAC) is presented in this paper. A bilateral output impedance compensation (BOIC) technique is proposed to suppress DAC nonlinearity induced by cell finite output impedance, which is compact, effective and power-efficient. Compensation networks are implemented by two NMOS transistors with code-dependent gate voltage. Furthermore, the calibration structure is improved to enable DAC cell bidirectional calibration, by designing the calibration DAC with a constant current source load. Simulation results in 22-nm CMOS show that The DAC achieves >65-dBc spurious-free dynamic range (SFDR) over the entire Nyquist bandwidth, with a 1.1V supply and an output swing over 0.9Vpp. The DAC core power consumption is only 37mW, showing its merits over state-of-the-art designs.

On-chip ESD (electrostatic discharging) protection is a challenging IC design problem. New CAD tools are essential to ESD protection design prediction and verification at the full chip level. This paper reports a new CAD tool, entitled ESDZapper, to simulate the complex ESD protection zapping test, procedures and to find the critical discharging path under a specific ESD stress. ESDZapper is developed based on a novel concept of ESD-critical parameters. Capability of the new tool is demonstrated using a practical design example in a 0.35μm BiCMOS technology.

On-chip electrostatic discharge (ESD) protection design is a challenging IC design problem. New computer-aided design (CAD) tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel smart parametric-checking mechanism and a new intelligent CAD tool, entitled ESD inspector, developed for full-chip ESD-protection circuitry-design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35-/spl mu/m BiCMOS technology.

The challenges for developing an on-chip electrostatic discharge (ESD) protection circuit layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extraction, and device count reduction. This paper reports a new technology independent layout extractor called the ESDExtractor, which is capable of extracting arbitrary ESD protection devices and answers the demands for full-chip ESD protection design verification. The general methodology to extract both intentional and parasitic ESD protection devices, the specific algorithms, and implementation methods to enhance ESDExtractor's efficiency are presented. Finally, the capability of the new computer-aided design tool is demonstrated using application examples.

The challenges for developing an ESD (Electro-static Discharge) layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extraction and device count reduction. This paper reports a new technology-independent layout extractor, ESDExtractor, which is capable of extracting all types of ESD devices and answers the demands for ESD design verification. General methodology to extract both intentional and parasitic ESD devices, specific algorithms and implementation methods for efficiencyenhancement are presented, followed by a design example.