Recent advances in sensing and computing technology have led to the proliferation of Cyber-Physical Systems (CPS) in safety-critical domains. However, the increasing device complexity, shrinking technology sizes, and shorter time to market have resulted in significant challenges in ensuring the reliability, safety, and security of CPS. This article presents a hybrid knowledge and data-driven approach for designing run-time context-aware safety monitors that can detect early signs of hazards and mitigate them in CPS. We propose a framework for formal specification of unsafe system context using Signal Temporal Logic (STL) combined with two optimization approaches for scenario-specific refinement and integration of STL specifications using data collected from closed-loop CPS simulations. We demonstrate the effectiveness of our approach in simulation using an autonomous driving system (ADS) and two closed-loop artificial pancreas systems (APS) as well as a publicly-available clinical trial dataset. The results show that a safety monitor developed with the proposed approaches demonstrates up to 4.7 times increase in average prediction accuracy (F1 score) over several well-designed baseline monitors while reducing both false-positive and false-negative rates in most scenarios.

Medical Cyber-physical Systems (MCPS) are vulnerable to accidental or malicious faults that can target their controllers and cause safety hazards and harm to patients. This paper proposes a combined model and data-driven approach for designing context-aware monitors that can detect early signs of hazards and mitigate them in MCPS. We present a framework for formal specification of unsafe system context using Signal Temporal Logic (STL) combined with an optimization method for patient-specific refinement of STL formulas based on real or simulated faulty data from the closed-loop system for the generation of monitor logic. We evaluate our approach in simulation using two state-of-the-art closed-loop Artificial Pancreas Systems (APS). The results show the context-aware monitor achieves up to 1.4 times increase in average hazard prediction accuracy (F1score) over several baseline monitors, reduces false-positive and false-negative rates, and enables hazard mitigation with a 54% success rate while decreasing the average risk for patients.

As a specific area of sensor networks, wireless in-home sensor networks differ from general sensor networks in that the network has nodes with heterogeneous resources and dissimilar mobility attributes. For example, sensor with different radio coverage, energy capacity, and processing capabilities are deployed, and some of the sensors are mobile and others are fixed in position. The architecture and routing protocol for this type of heterogeneous sensor networks must be based on the resources and characteristics of their member nodes. In addition, the sole stress on energy efficiency for performance measurement is not sufficient. System lifetime is more important in this case. We propose a hub-spoke network topology that is adaptively formed according to the resources of its members. A protocol named resource oriented protocol (ROP) was developed to build the network topology. This protocol principally divides the network operation into two phases. In the topology formation phase, nodes report their available resource characteristics, based on which network architecture is optimally built. We stress that due to the existence of nodes with limitless resources, a top-down appointment process can build the architecture with minimum resource consumption of ordinary nodes. In the topology update phase, mobile sensors and isolated sensors are accepted into the network with an optimal balance of resources. To avoid overhead of periodic route updates, we use a reactive strategy to maintain route cache. Simulation results show that the hub-spoke topology built by ROP can achieve much longer system lifetime.

Crossbar networks have been widely used as the interconnection mechanism in many multiprocessor/multicomputer systems. Crossbar networks can be categorized into three major topological classes: full-crossbar networks, multistage interconnection networks (MINs), and networks consisting of multiple levels of full crossbar connections, called hierarchical crossbar interconnection networks (HCINs). A significant amount of previous work exists in the area of performance modeling of systems with full-crossbar networks or multistage interconnection networks. However, performance modeling of multicomputer systems with HCINs has not been widely studied. This paper presents both analytical and simulation models for performance evaluation of an HCIN based on the commercial Mercury RACEway crossbar switch. The effective data transfer rate for message passing is taken as the primary performance metric and the models predict how this metric varies with the traffic load on the system. The analytical results are compared to the simulation results for different standard configurations of Mercury RACE Multicomputer Systems.

Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression. Although these computations lack the temporal locality of reference that makes traditional caching schemes effective, they have predictable access patterns. Since most modern DRAM components support modes that make it possible to perform some access sequences faster than others, the predictability of the stream accesses makes it possible to reorder them to get better memory performance. We describe a Stream Memory Controller (SMC) system that combines compile-time detection of streams with execution-time selection of the access order and issue. The SMC effectively prefetches read-streams, buffers write-streams, and reorders the accesses to exploit the existing memory bandwidth as much as possible. Unlike most other hardware prefetching or stream buffer designs, this system does not increase bandwidth requirements. The SMC is practical to implement, using existing compiler technology and requiring only a modest amount of special purpose hardware. We present simulation results for fast-page mode and Rambus DRAM memory systems and we describe a prototype system with which we have observed performance improvements for inner loops by factors of 13 over traditional access methods.

Processor speeds are increasing rapidly and memory speeds are not keeping up. Streaming computations (such as multimedia or scientific applications) are among those whose performance is most limited by the memory bottleneck. Rambus hopes to bridge the processor/memory performance gap with a recently introduced DRAM that can deliver up to 1.6 Gbytes/sec. We analyze the performance of these interesting new memory devices on the inner loops of streaming computations, both for traditional memory controllers that treat all DRAM transactions as random cacheline accesses, and for controllers augmented with streaming hardware. For our benchmarks, we find that accessing unit-stride streams in cacheline bursts in the natural order of the computation exploits from 44-76% of the peak bandwidth of a memory system composed of a single Direct RDRAM device, and that accessing streams via a streaming mechanism with a simple access ordering scheme can improve performance by factors of 1.18 to 2.25.

It is well known that techniques such as performance modeling that can effectively evaluate design alternatives early in the design process can greatly increase the quality of the ultimate implementation, while at the same time, decrease the design time. In order to gain the maximum benefit from performance modeling, it must be integrated into the design process such that the performance model can be directly refined into an implementation. This paper presents techniques for developing interfaces between abstract performance models and detailed behavioral models to enable this refinement process. These mixed-level modeling interfaces, as they are called, allow abstract performance models to be cosimulated with detailed behavioral models. Because of the differences in the level of detail between abstract performance models and detailed behavioral models, not all of the inputs to the behavioral model can be derived from information in the performance model. Techniques for determining values for these "unknown" inputs are presented, These techniques have been designed to generate bounds on the system performance that converge as the model is refined.

This paper presents a design environment for cycle-based systems, such as microprocessors, that permits modeling of these systems at various levels, from the abstract system level, through the detailed RTL level, to an actual implementation. The environment allows the models to be refined to lower levels in a step-wise manner. The environment provides the ability to obtain meaningful metrics from abstract models of a processor's architecture. This capability allows design alternatives to be evaluated earlier in the design cycle, thus eliminating costly redesign and reducing the processor time to market.

This paper presents an integrated design environment thatsupports the design and analysis of digital systems from initialconcept to the final implementation. The environment supports bothsystem level performance and dependability analysis from acommon modeling representation. A tool called ADEPT (AdvancedDesign Environment Prototype Tool) has been developed toimplement the environment. ADEPT is based on IEEE 1076 VHDLand uses commercial schematic capture systems as a front end viaan EDIF interface. Several examples are presented whichdemonstrate various aspects of the environment.

Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression. Although these computations lack the temporal locality of reference that makes caches effective, they have predictable access patterns. Since most modern DRAM components support modes that make it possible to perform some access sequences faster than others, the predictability of the stream accesses makes it possible to reorder them to get better memory performance. We describe and evaluate a Stream Memory Controller system that combines compile-time detection of streams with execution-time selection of the access order and issue. The technique is practical to implement, using existing compiler technology and requiring only a modest amount of special-purpose hardware. With our prototype system, we have observed performance improvements by factors of 13 over normal caching. 1. INTRODUCTION...

Generation of test vectors for the VLSI devices used in contemporary digital systems is becoming much more difficult as these devices increase in size and complexity. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Since ATPG is an NP complete problem with complexity exponential to circuit size, the application of parallel processing techniques to accelerate the process of generating test vectors is an promising area of research. The simplest approach to parallelization of the test generation process is to simply divide the processing of the fault list across multiple processors. Each individual processor then performs the normal rest generation process on its own portion of the fault list, typically without interaction with the other processors. The major drawback of this technique, called fault partitioning, is that the processors perform redundant work generating test vectors for faults covered by vectors generated on another processor. This problem has been solved with the introduction of dynamic load balancing and detected fault broadcasting. Previous research has indicated that algorithmic fault partitioning moderately improves the performance of fault partitioned ATPG without detected fault broadcasting by reducing redundant work. However algorithmic fault partitioning can add significant preprocessing time to the ATPG process. This paper presents results that show that algorithmic partitioning is unnecessary prior to fault partitioned parallel ATPG using detected fault broadcasting and dynamic load balancing. Considering preprocessing time, random fault partitioning is shown to be the most efficient technique for partitioning faults prior to fault partitioned ATPG.

Generation of test vectors for the VLSI devices used in contemporary digital systems is becoming much more difficult as these devices increase in size and complexity. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Since ATPG is an NP complete problem with complexity exponential to circuit size, the application of parallel processing techniques to accelerate the process of generating test vectors is an active area of research. The simplest approach to parallelization of the test generation process is to simply divide the processing of the fault list across multiple processors, Each individual processor then performs the normal test generation process on its own portion of the fault list, typically without interaction with the other processors. The major drawback of this technique, called fault partitioning, is that the processors perform redundant work generating test vectors for faults covered by vectors generated on another processor. An earlier approach to reducing this redundant work involved transmitting generated test vectors among the processors and fault simulating them on each processor. This paper presents a comparison of the vector broadcasting approach with the simpler and more effective approach of fault broadcasting. In fault broadcasting, fault simulation is performed on the entire fault list on each processor. The resulting list of detected faults is then transmitted to all the other processors. The results show that this technique produces greater speedups and smaller test sets than the test vector broadcasting technique. Analytical models are developed which can be used to determine the cost of the various parts of the parallel ATPG algorithm. These models are validated using data from benchmark circuits.

The design of complex systems requires an enormous amount of modeling and simulation at the various levels of detail to assure high quality results. Most design methodologies require the use of separate modeling languages and simulation environments for each refinement step and simulation technique. Since one of the major goals of design is to reduce the time to market for a given system, the current approaches are becoming unacceptable. A new unified modeling (UM) methodology is under development at the University of Virginia which provides a top-down/bottom-up design methodology based on a single modeling environment. This single environment methodology is made possible through a technique known as hybrid modeling, which enable the simulation and analysis of behavioral components within a system-level model. By simulating behavioral components along with components at the system modeling level, high risk portions of the design can be examined at earlier stages in a given product's development; thus reducing the time to market. The paper examines the hybrid modeling techniques which make this multi-level modeling possible.

This paper presents preliminary results of research being conducted in the application of distributed/parallel algorithms to automatic test pattern generation for synchronous sequential circuits. The system is required to be portable across a wide variety of architectures -from workstations to dedicated parallel machines. This requirement necessitates the use of a parallel programming environment that provides a layer of abstraction between the application and the hardware. The first phase of the proposed system involves generation of circuit covers - input patterns that control the circuit outputs.

Generation of test vectors for the VLSI devices used in contemporary digital system is becoming much more difficult as these devices increase in size. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Since ATPG is an NP complete problem with complexity exponential to circuit size, the application of parallel processing techniques to accelerate the process of finding test patterns is an active area of research. This paper presents an approach to parallelization of the test generation problem that is targeted to a network-of-workstations environment. The system is based upon partitioning of the fault list across multiple processors and includes enhancements designed to address the main drawbacks of this technique, namely unequal load balancing and generation of redundant vectors. The technique is generalized enough that it can be applied to any test generation system regardless of the ATPG or fault simulation algorithm employed. Results were gathered to determine the impact of workstation processing load and network communications load on the performance of the system.>

Generation of test vectors for the VLSI devices used in contemporary digital systems is becoming much more difficult as these devices increase in size. Automatic Test Pattern Generation (ATPG) techniques are commonly used to generate these tests. Parallel processing techniques can be applied to accelerate the process of finding test patterns. One problem with this approach is that most currently available distributed memory multicomputers have a limited amount of memory on each processor which limits the size of the circuit database that can be contained on a single node. Topological partitioning of the circuit database across several processors can increase the size of VLSI circuits that can be processed on a given parallel machine. This paper presents the architecture of a topologically partitioned ATPG system and several partitioning algorithms that can be used to partition the circuit-under-test. This paper also presents several parallelization methods that may be applied to topologically partitioned ATPG on a distributed memory multicomputer. Results of using these parallelization techniques along with topological partitioning are presented.>

The increasing size and complexity of current VLSI circuits has brought testing and design for testability into the mainstream of the design process. A significant amount of research has been done in the area of gate-level combinational ATPG using the stuck-at-fault model. The problem has been shown to be NP-complete and most of the current research attempts to find efficient ways to generate tests for hard faults in a reasonable amount of time on the average. Hence, there remains a lot of interest in the testing world for efficient techniques to do combinational ATPG. Use of ordered binary decision diagrams (OBDDs) for function representation has provided significant impetus to algebraic CAD techniques. This paper presents techniques for gate-level ATPG using OBDDs.>

As the scope of application of embedded CPUs changes, the design methodologies used to create embedded systems must keep pace. The authors explore what is understood of embedded system design, what problems need to be solved, and novel technologies that may help solve those problems.>

There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The single path design methodology presented is a possible solution to this problem. The basic concept of the methodology is the use of one simulation language, the VHSIC hardware description language (VHDL, Version 1076) for all phases of design. The VHDL framework allows for iterative stepwise refinement of a model. A performance (uninterpreted) model can be refined to a register transfer level (RTL) description without changing modeling environments or completely rewriting the models. As an example, the performance-modeling phase of the single path design methodology is applied to the WM machine, a superscalar computer architecture.>

A novel methodology is presented which allows the creation of implementation-independent functional models of systems. The methodology uses the VHSIC (very high speed integrated circuit) hardware description language (VHDL) which leads to the possibility of creating a unified design environment supporting system modeling at various stages of the design process. The motivation for the methodology was to assist in the analysis and specification of the WM computer architecture. An implementation-independent model of the WM architecture is provided which is intended as a first step in the development of an implementation. Additionally, architectural performance measures can be extracted from simulations using the model. The model can also serve as an architectural specification for the WM computer.>

A technique using genetic algorithms is presented for the generation of compact test sets for combinational VLSI circuits. The technique combines a previously proven method for random test pattern generation with adaptive searching capabilities to produce high-quality test sets. A series of experiments demonstrated that the technique performed consistently better than the traditional method. On average, the method is able to produce test sets that are approximately 20% smaller than the starting configuration. To place this in perspective, its solutions are on average 13% more compact than those produced by a traditional method with no loss in fault coverage.>

A concurrent error detection and design for testability technique based on conservative logic is presented. The theoretical derivations and experimental results show that conservative logic provides inherent support for concurrent error detection, and the resulting circuits can be tested using only two test patterns, independent of the function performed by the circuit. The background definitions are presented, and the fundamental conservative logic theory is developed. Several example designs of adder and multiplier circuits are presented and analyzed to illustrate the developed theory. A possible implementation of a conservative logic gate is presented, and its use in a VLSI circuit is described. The resulting circuit has been fabricated using the MOSIS process. The primary disadvantage of the approach is shown to be the implementation technology.>

The authors discuss methodologies and tools that allow a system to be analyzed using Petri nets or queuing models. Models at this level contain tokens rather than values, and the function of blocks remains undefined. Such analysis is performed early in the design process to evaluate overall system performance. Different methodologies and tools are available to allow design analysis and verification at interpreted levels through hardware design language (HDL) descriptions. Tokens are replaced with specific values for the representation of signals. The methodology presented allows the designer to create uninterpreted models in an environment already capable of interpreted modeling, the VHSIC hardware description language (VHDL). Uninterpreted modeling in an HDL is the first step in the creation of a continuous single-path design environment.>

Analysis approaches that can be used in the design of computer-based systems for medical applications are described. The major contributions are the definition of safety and the development of analysis techniques which allow safety to be quantified. The results presented are of particular importance in medical applications where the inappropriate operation of the computer system can be catastrophic. A microprocessor-based controller developed for an electric wheelchair is described and used as an example to illustrate the basic concepts and modeling techniques. The results demonstrate that reliability considerations alone are insufficient to evaluate the effectiveness of a given design; safety must also be considered to ensure that the best design is selected for a given application.>