A new approach to customer-oriented end-to-end testing is proposed as an integral part of the architecture for enhancing the reliability of AT&T Bell Labs' products and the quality of their ISDN services. The basic idea is to create virtual customers who are constantly using the system as real customers, thereby continually exercising and monitoring the system's operations in a real working environment. Any potential system problem will thus be detected first by the virtual customers. Therefore, problems are expected to be corrected before any reaction from the paying customers. Such a proposal appears to be relatively simple. The important question concerns whether one can emulate the customers who can effectively set up end-to-end dialogs as done by real customers. The objective of this experiment on the 5ESS (electronic switching system) is to apply this technique to implement virtual customers as a means of on-line, real-time testing of the system's capability in providing high quality customers services. Although a very limited data collection has been taken, the on-line customer-service-oriented testing approach has been demonstrated to be an effective means of uncovering difficult problems in a real system environment.>

In designing a self-checking processor, it is essential to recognize the types of failures that are most probable. Matching the checking techniques with the type of faults that are expected to occur should yield the best result with the least amount of hardware. The microprogram control will consist of integrated circuits: large-scale integration (LSI) for the memory and small-scale integration (SSI) for the associated control logic. Because of the density of chips on a plug-in package and the physical proximity of the devices on an integrated circuit, multiple faults within a single circuit are highly probable. The types of faults within a circuit have been analyzed and found to be of the type which would tend to affect the bits in a unidirectional manner. Also the failed bits would probably be adjacent rather than randomly dispersed throughout-the microprogram store word.

In binary counters, the parity bit is not preserved when the data undergo the counting operation. It is necessary to predict the parity bit that should be used with the correct result. A special design has been devised to share as much hardware as possible between the counter and the parity prediction circuit. This reduces the number of logic gates and gives a more efficient design. The scheme involves the use of the first 0 detection for both the counting operation and the parity prediction.

This paper describes a modular approach of implementing the control circuitry. It is achieved by the use of multifunctional binary decoder circuits in conjunction with a transistor array high-speed READ-ONLY memory.

The choice of fault detection methods to be used in control and data transfer circuits is strongly dependent on system organization. This paper presents a unified parity check scheme for both.

A bidirectional gate is described which would allow information contained in one register to be transferred to another register or vice versa. The rotate/shift functions may be implemented by gating the data between two flip-flop registers through the shifted or skewed gates connecting the two. The unique property of bidirectional transfer of data signals between two registers permits a simplified and interesting design of a rotate and shift circuit. The implementation of this rotate/shift circuit into a data processing configuration is also illustrated.