The authors propose an algorithm for automatically generating a mask pattern from the logical description of a large-scale CMOS circuit, i.e., 'macro', consisting of up to several thousands of transistors. The layout model considered is a 2-D or 'multi-row' model which is composed of a set of rows of paired PMOS and NMOS transistors. The large-scale layout synthesis is attained by combining an effective 1-D layout synthesis and a standard cell layout algorithm in divide-and-conquer style. For a practical circuit, the proposed algorithm yields an 18% smaller layout than the conventional standard cell approach.>

This paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size designed by using the proposed layout method is only 1.2-1.4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective for achieving a minimal chip layout design.

This paper describes an automatic/interactive layout design system for designing master-slice LSI chips, which places function blocks and gives wiring patterns on the chip. Since 100% routing is essential for master-slice layout design, it is urgently required to establish a strong CAD system, which significantly reduces the design time. The LAMBDA system has been developed to achieve complete net connectivity in as short a design time as possible, where efficient automatic procedures are implemented as well as highly interactive functions. The system adopts two-level hierarchy algorithms for placement and routing problems. Highly interactive functions are realized by exploiting human intelligence and the computer's high speed processing.