A television-based computer display system is described which uses a minicomputer to calculate scan lines of the display image. A display resolution of 512 lines by 512 positions is achieved with each position definable with 15 bits of color information (over 32,000 colors). The scan conversion process incorporates hidden surface removal, calculation of intersections, surface shading and, optionally, perspective. Object description must be by polygonal planar surfaces; the surfaces can have a solid color and are considered opaque. Object complexity is limited only by main storage size.The design criteria which motivated the system architecture are discussed along with pertinent details on the particular implementation. The system described effectively mates minicomputer technology with that of the television industry to produce an economical, fast turnaround, color display system for 2-D and 3-D computer graphics. This system relies upon a special scan-line generator and upon a skillful hardware/software trade-off to achieve an economical and realistic color display device.Performance data and examples of display objects are given.

A detailed study of the basic operations of scan graphics processes led to the design of this general-purpose expandable processor. Full advantage is taken of evolving trends in ECL technology and large-scale integrated circuits. The design allocates hardwired instructions to critical display functions and provides general-purpose flexibility in externally microprogrammable asynchronous processors. The machine uses instruction set partitioning and is optimized to execute relatively short programs operating on large data bases. The processor is thus not limited to display generation but is rather well suited for other real-time tasks, particularly those operating with autonomous processors which can be added as external devices.

A class of critical computer requirements for real-time scan T.V. computer graphics is examined in relation to commercially available CPU architectures. Finding general purpose processors not suited, a new processor is proposed which is designed around the concept of "instruction set partitioning." In this design, special hardware-implemented algorithms may be included in the machine instruction set, and these processors allowed to operate asynchronously from each other. The design is projected to generate a complete new frame of a color T.V. picture every 0.1-0.8 seconds depending on image complexity. Due to its inherent generality, the CPU may be similarly expanded to encompass a wide variety of other specialized, or real-time tasks with minimal additional hardware. The 32-bit parallel processor has a design cycle time of 100 ns and is in the price class of a minicomputer.