In this work, an 8-to-24 GHz 6-bit bidirectional Common-Chain (CC) is presented that enables low noise, wide bandwidth (BW) compact core-chip in SiGe BiCMOS with low power dissipation. The chain contains phase shifter (PS), attenuator and HBT based active bidirectional amplifiers (BDAs). The PS is designed considering multiple resonance frequencies for an improved BW. The attenuator’s device sizes are determined for low phase variation. The loss of these blocks are tolerated by BDAs, which are also utilized to generate new LSBs for phase and amplitude control. The CC succeeds 16.12 dB peak gain at 21.5 GHz and + 2.58dB/BW of a gain slope. It achieves a mean 4.41°/0.4dB RMS errors for 16 GHz of BW, while dissipating 55 mW of power in a 3.28 mm2area. To the best of authors’ knowledge, this work succeeds the best gain, noise, resolution, and SWaP-C features for 100% of fractional BW in SiGe BiCMOS.

A two-step approach is introduced to reduce the overshoot voltage and increase the speed of the zero-crossing detector (ZCD) in a SAR-assisted pipeline ADC. The technique detects the zero-crossing of the input without reducing the speed of the current source and thereby, achieves a minimum overshoot voltage with improved speed. The proposed technique achieves a maximum of 2.8 mV of overshoot voltage with an amplification time of 1.34 ns. The proposed technique is implemented in an 8b radix-1.8 $\mathrm{V}_{\mathrm{cm}}$-based SAR-assisted two-stage pipeline ADC in 130 nm SiGe BiCMOS technology. The post-layout simulation results achieve an ENOB of 7.3965 bits and 6.7667 bits that corresponds to an SNDR of 46.287 dB and 42.287 dB with a sampling rate of 20 MS/s at an input frequency of 1.3021 MHz and at the Nyquist frequency, respectively.

This paper presents a low-noise 320 × 240 digital readout integrated circuit (ROIC) for SiGe microbolometers with a pitch size of 17 μ m. The ROIC architecture uses a column-shared capacitive transimpedance amplifier (CTIA) that senses the change in resistance of the SiGe microbolometers with respect to the column-shared reference microbolometer pixel. The output voltage of the CTIA is then digitized using a split-successive approximation register (SAR) analog-to-digital converter (ADC). Each 40 columns of the CTIA is connected to a SAR ADC with the help of a 40×1 MUX, which makes 8 parallel-operating ADCs in total. In this way, speed and power requirements of ADCs are relaxed. The offset calibration for the comparator, in the split-SAR ADC is designed using a novel two-step coarse and fine current adjusted technique. The prototype ROIC consumes 118.75 μW power per column while has an NETD of less than 9mK. Simulation results of the proposed offset-calibration technique offers a minimum conversion time of 71.78 ns with a minimum residual voltage of 42 μ V.

This paper presents a step variable attenuator with 0.22 dB flat attenuation states and low phase variation between 1.5-13.5 GHz. This work consists of 7 switched ΠT-type attenuation blocks. The parasitic effects of conventional NMOS transistors degrade the performance of attenuators in terms of insertion loss and attenuation flatness. Therefore, isolated NMOS (iNMOS) devices were preferred instead of conventional NMOS devices to utilize switching to improve RF performance. Also, attenuation states degrade at higher frequencies. Thus, a parallel capacitor was inserted in each Π-type attenuation bits to achieve flat attenuation states. This chip was designed and fabricated with IHP Microelectronics 0.13 μm SiGe BiCMOS technology. The measured attenuator can cover 28 dB with 0.22 dB incremental states. The root mean square (RMS) amplitude error of this chip is less than 0.22 dB between 2 to 9.5 GHz. The RMS amplitude error at 13.5 GHz is 0.27 dB. RMS phase error was measured less than 2.5° between 1.5-13.5 GHz. The measured input referred 1-dB compression point (IP1dB) of the attenuator is 12 dBm at 7.5 GHz. The insertion loss (IL) of the fabricated attenuator was measured less than 15.8 dB. The dimensions of the fabricated chip are 1.592*0.793 mm2.

This paper presents a speed-enhanced asynchronous SAR control logic, based on a two-phase handshake architecture. The control logic comprises of logic cells. Each logic cell employs a static logic gate and an SRAM-latch. The interaction between them, based on a two-phase handshake architecture, supports high-speed output change. The SAR control logic is implemented in a 6b Vcm-based successive approximation register (SAR) analog-to-digital converter (ADC) with 1b redundancy in 90 nm bulk CMOS process. Based on the post-layout simulation result, the propagation delay for one bit of conversion by the proposed control logic is 0.24 ns. The power consumed by the SAR control logic is 0.99 mW with 1.2 V supply. The post-layout simulation results for the SAR ADC show an SNDR/SFDR of 36.2 dB and 44.13 dB, respectively at 500 kS/s sampling rate with an input frequency of 54.68 kHz. The simulated differential and integral non-linearity (INL and DNL) are 0.38 LSB and 0.24 LSB, respectively.

Digital readout integrated circuits (DROICs) for small pitch infrared focal plane arrays (IR-FPAs) suffer from low in-pixel resolution owing to the limited pixel real estate. To this end, a new technique to improve the resolution of pulse frequency modulation (PFM) based pixels, using quantization charge noise shaping, is presented. Multiple integration operations are performed in a single frame and the quantization error from each integration phase is retained and effectively induced into the next integration phase. The result is a high pass noise transfer function (NTF) equivalent to what is obtained in a first order sigma delta modulator. Along with a theoretical analysis of the technique, a prototype based on a single pixel and a 2ndorder decimation filter is developed to demonstrate the performance of the proposed technique. With an in-pixel circuitry generating 5 bits, a resolution of 11 bits (65 dB) is achieved with an over-integration ratio of 64. With a 100 Hz frame rate and 64 integration operations per frame, a readout noise of 1100e- is measured at full-well fill from the test pixel fabricated in a 90nm CMOS process.

This paper presents a hand-held point-of-care diagnostic device that incorporates a lab-on-a-chip module with interdigitated capacitive biosensors for label-free detection of multiple cancer and cardiovascular disease biomarkers. The developed prototype is comprised of a capacitive bio-detection chip, a sensitive capacitive readout electronics enclosed in a hand-held unit and a data analysis software calculating the quantity of biomarkers using previously stored reference database for different concentrations of each biomarker. The capacitive bio-detection chip is based on interdigitated circular electrodes, which are pre-activated with single (for detecting one biomarker) or multiple specific antibodies (for detecting multiple disease biomarkers). Detection principle of capacitive biosensor is based on measuring the level of capacitance change between interdigitated electrode pairs of the capacitive biosensor chip induced by the change in dielectric constant due to affinity-based electron exchange in between antibodies and antigens. The more antibody-antigens binding occurs, the more capacitance change is measured due to the change in dielectric constant of the capacitance media. The device uses pre-activated ready-to-use cartridges, composed of capacitive biosensors, which can be stored 3 months under optimal conditions, and is capable of on-site diagnosis and can report the result in less than 30 minutes. The device is verified with 16 real patient blood samples for 6 different disease biomarkers.

This paper focuses on achieving high dynamic range pixel by using multiple pre-amplifiers in the pixel. There are two input circuits which are optimized for different signal levels inside the pixels. A smart circuit mechanism, inside each pixel, decides the best input circuit according to the incoming light level. In short, an individual pixel has the ability to select the best input amplifier circuit that performs the best SNR for the incoming signal level. A prototype chip is designed in 0.18 um CMOS technology. Pixel can achieve minimum 8.6 e-input referred noise and 98.9 dB dynamic range. In room temperature, power consumption of 2.8 uW is measured for the pixel.