Photoplethysmography (PPG) has been widely used in consumer and medical devices for assessing heart rate blood oxygen and blood pressure levels, together with electrocardiography (ECG). One of the major challenges is recording PPG with fast changing ambient light and motion artefacts that generating a changing baseline of the signal. Light to digital converters (LDCs) proposed in recent years show excellent resolution and power efficiency, however it may get saturated during fast ambient and motion events. Existing chopping ambient light removal and hysteresis DC removal techniques cannot track fast-changing components. Therefore, this paper proposes a current domain level crossing-based technique to assist a dual slope LDC, including a dynamic biased low-power continuous time comparator. The PPG readout frontend is implemented in a 55nm standard CMOS process and consumes 12.4μW-56.6μW depending on the ambient light intensity. It achieves a dynamic range of 102dB and an SNDR of 75dB at AC signal path.

This paper proposes a dual-mode AFE system that supports both voltage and electrochemical impedance spectroscopy (EIS) monitoring for multiple cell Li-ion batteries. The proposed current-balanced IA adapts the common mode voltage of the selected cell by taking the same voltage from the same cell, enabling multiple cell monitoring with minimum current. The system also includes a DC-servo loop cancelling the DC component from the AC voltage excited by a current generator. To the best of the author’s knowledge, it is the first BMS AFE system supporting multiple cell EIS monitoring, providing better SoC/SoH estimation and safety for Li-ion batteries.

This article presents a two-stage pipelined noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converters (ADCs) for sub-micro-watt and high-resolution applications. However, it asks for an accurate residue amplification to avoid severe quantization noise leakage from the frontend stage. Therefore, a charge-efficient correlated-level-shifting (CECLS) assisted residue amplifier (RA) is designed by inserting the level-shifting network (LSN) in a two-stage floating inverter amplifier (FIA). In addition to the inherited low-power merit from FIA, it boosts the equivalent open-loop gain to 92 dB while preventing bandwidth reduction and charge-sharing effects, making the amplification more accurate and faster than prior CLS-assisted amplifiers. The prototype is fabricated using 55 nm CMOS technology and occupies an active area of 0.26 mm$^{\mathbf {2}}$. The measurement results show a 96.2 dB peak-SNDR and 871 nW power consumption under a 1.2 V supply voltage with a 16 kS/s sampling rate. Compared to the recent state-of-the-art ADCs with power under$10\mu $W and SNDR exceeding 90 dB, this ADC presents the best Schreier FoM of 180.8 dB.

A constant off-time (COFT) based current-balancing (CB) technique is proposed for integrated multi-phase DC-DC switching regulators with wide input/output (I/O) voltage range. The small-signal characteristics and design criteria of the proposed technique are derived based on describing functions. The current-balancing accuracy of the proposed technique depends merely on the ratio between the sensing FETs and the corresponding power switches ($\alpha $), while the requirement on absolute equivalent sensing-resistances ($R_{\mathrm {i}}$) and the matching of sensing circuits among phases are relaxed. Meanwhile, both the proposed current-balancing behavior and the adjustment of phase number will not affect the stability and the transient behavior of the multi-phase system. Furthermore, as a crucial block of the COFT control scheme, the proposed self-tuning PLLs of clock synchronization loop can remain fixed bandwidth under different I/O voltages, which further enhance the system stability. Therefore, in principle, the phase-interleaving with fixed switching frequency can be realized without the limit of duty cycle. As a result, the proposed CB technique can alleviate the stringent matching requirement of layout in conventional multi-phase systems, as well as the loop compensation difficulty. It is verified by an integrated dual-phase regulator fabricated in a$0.18\mu $m BCD process. Experimental results show that the regulator can provide 0.9-1.8V output from a 2.3-5.5V input at both steady state and load-transient state with significantly higher performance by the proposed CB technique, ensuring current-imbalance ratio within ±1.3%.

To achieve high efficiency over wide load range for modern mobile applications, this brief proposes a ripple-based V2-controlled buck converter operating with pulsewidth modulation (PWM)/pulse-frequency modulation (PFM)/load-adaptive standby mode (LASM). On system level, a delay-based load-adaptive V$_{\text {ON}}$generator is exploited in LASM at ultralight load. When the output ripple is kept below its maximum restriction, the switching loss of the converter is further minimized in LASM compared with prior operation modes, including PFM, pulse-skip modulation (PSM), multiple-sawtooth PWM (MSPWM), and deep green mode (DGM). On circuit level, a dynamic-biased dual-offset hysteresis comparator is proposed. Together with other blocks that can be disabled, the quiescent consumption of controller in LASM is reduced to only 14$\mu $W. Fabricated in a 130-nm BCD process, the proposed converter can provide a 1.8-V output with a power density of 4.11 W/mm2. It achieves a 93.2% peak efficiency, while the efficiency can be maintained above 86.4% in 1 mW–10 W ($\times 10~000$) load range.

This paper presents a low-power chopper-stabilized capacitively-coupled frontend amplifier with auxiliary-path-based input impedance ( Z$_{\mathbf{in}}$) boosting. In order to achieve a high Z$_{\mathbf{in}}$, a low noise and a small chip area, techniques on both system level and circuit level are implemented. On the system level, small capacitors ( C$_{\mathbf{in}}$$=$0.5 pF, C$_{\mathbf{fb}}$$=$25 fF) are used with a biased pseudo-resistor ( R$=$2.5 G$\Omega $) fed back to an amplifier internal node. As a result, a high achievable Z$_{\mathbf{in}}$and low high-pass corner frequency are achieved. On the circuit level, an input capacitance shielded current feedback (CSCF) topology achieving effective 10 fF C$_{\mathbf{amp}}$is proposed as the core of the capacitive feedback amplifier in order not to increase the input noise. Moreover, the design space of auxiliary-path-based boosting is explored to obtain the optimal value of buffer bandwidth and auxiliary capacitor size to save power. The amplifier and its Z$_{\mathbf{in}}$boosting circuit are implemented in a standard 55 nm CMOS process and characterized experimentally. Measurement results show that the proposed amplifier provides an input noise density of 50 nV/$\surd$Hz, and an integrated noise of 0.85$\mu$V$_{\mathbf{rms}}$in 200 Hz band. The Z$_{\mathbf{in}}$is boosted to 1.92 G$\Omega $at DC and 1.02 G$\Omega $at 50 Hz with only 1.0$\mu$A in each auxiliary path buffer. The amplifier also archives 77 dB CMRR and 76 dB PSRR while consuming 20.3$\mu$W in total.

A 1V 56.07dB SNDR 10MHz bandwidth digital slope ADC based on Preset Bidirectional-Shifting Technique is presented. With the proposed Preset Bidirectional-Shifting Technique, the number and conversion time are decreased impressively. Under low input frequency, the structure can achieve high resolution and high speed. Moreover, passive noise-shaping is used to implement an on-chip correction for the comparator latency. The proposed ADC is simulated in a 55nm CMOS process, achieving an SNDR of 56.07dB and consuming 941μW with a 1V supply. The simulation achieved a Schreier FoM of l56.33dB.

An ultra-low quiescent current tri-mode DC-DC buck converter is presented in this paper, which is able to handle a 100,000X load range. In pulse width modulation (PWM) and pulse frequency modulation (PFM) mode, adaptive on-time (AOT) V2control is utilized to achieve seamless mode transition and constant switching frequency in PWM mode. A deep green mode (DGM) is proposed for light load, where both the switching loss and the power of control circuitry are minimized. By reducing the comparator current, a delay-based hysteresis window adaptive to load current is generated, reducing the switching frequency and the loss. Meanwhile, the average current of zero current detector (ZCD) and AOT controller are reduced significantly by dynamic biasing. As a result, the efficiency of the converter is improved while maintaining a reasonable output ripple. The proposed converter is implemented in a$0.18\mu $m BCD technology. Experimental results show that the converter can provide a 1.6 V output from a 2.7 to 4.7V input for$1\mu $A to 100 mA load, while consuming only 490nA quiescent current. The proposed converter achieves a 92.1% peak efficiency and efficiency can be maintained above 80% in a load range of$20\mu $A to 60 mA.

This paper proposes a multiple-channel frontend system with current reuse for fetal monitoring applications. The structure and specifications of the proposed frontend system are determined while taking into consideration the algorithms used for fetal electrocardiogram (fECG) detection. Two amplifier topologies based on a middle rail current source/sink (MCS) are proposed for fECG and electrohysterogram (EHG) recording. The proposed amplifiers explore power optimization in both current and voltage domain and thus achieve a better effective noise efficiency factor (NEF) while providing multiple-channels. The frontend system is designed in a 0.18μm CMOS process. Simulation results show that the frontend system provides 3 fECG and 4 EHG recoding channels with a total power consumption of 3.1μW. The IA for fECG monitoring achieves an equivalent NEF of 1.17/1.21 for low noise and low power settings respectively.

This paper proposes a low-power noise scalable instrumentation amplifier (IA) for fetal monitoring applications. The noise specification of the IA is made adaptive to the peak-peak value of the fetal electrocardiography (fECG) signal, which varies for different gestational age and measurement settings. Contrary to the currently available point solution IAs, the proposed IA is scalable for a noise range from 30nV/VHz to 250nV/VHz while consuming 15μW to 1μW respectively. A new IA architecture is proposed to achieve a better noise efficiency factor (NEF), while allowing noise scalability. The IA is designed in TSMC 0.18μm CMOS process. Simulation results show that the IA achieves a NEF of 3.4 to 5.5 over the noise scalable range, a CMRR of 100dB, and an input impedance (Zin) of 1GO.