Complexity in parallel computation for current HPC systems has being modeled in order to estimate time and energy consumption, which have been conduced to evaluate real costs. Communication analytical models for time and energy comsumption are an attractive issue as part of this cost analysis in parallel computation. In this paper, we present time and energy analytical models for MPI communications using OSU micro benchmarks under Sandy Bridge-EP computer architecture. RAPL (Running Average Power Limit) interface has been setup to provide mechanisms to enforce real energy consumption measurements for OSU micro benchmarks on this architecture. Our applied methodology defines an experimental framework based on several core configurations and different transmission rates. The RAPL interface allows us to obtain different energy values for the OSU benchmark executions. The measures obtained are used to obtain time and energy consumption parameters of our models, establishing average errors below 1% for almost all configurations in real executions under this computer architecture for an ad-hoc model. Alternative and simpler time and energy models are also proposed with errors up to 3.1% for the worst case.

Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed architectures replace a re-order buffer (ROB) with a check-pointing mechanism and an out-of-order release of processor resources. Check-pointing, however, leads to an imprecise processor state recovery on mis-predicted branches and exceptions and re-execution of correct-path instructions after state recovery. It also requires large register files complicating renaming, allocation and release of physical registers. This paper proposes a new processor architecture called a Multi-State Processor (MSP). The MSP does not use check-pointing, avoids the above-mentioned problems, and has a fast, distributed state recovery mechanism. The MSP uses a novel register management architecture allowing implementation of large register files with simpler and more scalable register allocation, renaming, and release. It is also key to precise processor state recovery mechanism. The MSP is shown to improve IPC by 14%, on average, for integer SPEC CPU2000 benchmarks compared to a check-pointing based mechanism ([2]) when a fast and simple branch predictor is used. With a very aggressive branch predictor the IPC improvement is 1%, on average, and 3% if some of the programs are optimized for the MSP. The MSP also reduces the average number of executed instructions by 16.5% (12% for the aggressive branch predictor), mostly due to precise state recovery. This improves the MSP processor energy efficiency even though it uses a larger register file.