Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor implemented in today's technology can achieve an increase of 10-60% (geometric mean of 31%) in program speed compared to today's processors. The processor operates at clock speeds comparable to today's processors, but achieves significantly higher ILP.

The poor scalability of existing superscalar processors has been of great concern to the computer engineering community.In particular, the critical-path lengths of many components in existing implementations grow as O(n') where n is the fetch width, the issue width, or the window size.This paper describes two scalable processor architectures, the Ultrascalar I and the Ultrascalar II, and compares their VLSI complexities (gate delays, wire-length delays, and area.)Both processors are implemented by a large collection of ALUs with controllers (together called execution stations) connected together by a network of parallel-prefix tree circuits.A fattree network connects an interleaved cache to the execution stations.These networks provide the full functionality of superscalar processors including renaming, out-of-order execution, and speculative execution.The difference between the processors is in the mechanism used to transmit register values from one execution station to another.Both architectures use a parallel-prefix tree to communicate the register values between the execution stations.The Ultrascalar I transmits an entire copy of the register file to each station, and the station chooses which register values it needs based on the instruction.The Ultrascalar I uses an H-tree layout.The Ultrascalar II uses a mesh-of-trees and carefully sends only the register values that will actually be needed by each subtree to reduce the number of wires required on the chip.The complexity results are as follows: The complexity is described for a processor which has an instruction-set architecture containing L logical registers and can execute n instructions in parallel.The chip provides enough memory bandwidth to execute up to M(n) memory operations per cycle.(M is assumed to have a certain regularity property.)In all the processors, the VLSI area is the square of the wire delay.The Ultrascalar I has gate delay O(log n) and wire-delayj2), and O(fiL + M(n)) if M(n) is 0(nli2+') 'This work was partially supported by NSF Career Grants CCR-9702980 (Kuszmaul) and MIP-9702281 (Henry) and by an equipment grant from Intel.Permission to make digital or hard copies of all or part of this work for personal or classroom USC is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the tirst page.To copy otherwise, to republish, to post on servers or to redistribute to lists.requires prior specific permission and/or a fee.

Article Free Access Share on A tightly-coupled processor-network interface Authors: Dana S. Henry View Profile , Christopher F. Joerg View Profile Authors Info & Claims ASPLOS V: Proceedings of the fifth international conference on Architectural support for programming languages and operating systemsSeptember 1992 Pages 111–122https://doi.org/10.1145/143365.143497Published:01 September 1992Publication History 80citation599DownloadsMetricsTotal Citations80Total Downloads599Last 12 Months34Last 6 weeks8 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF