High speed chip-to-chip communication links suffer from attenuation and inter-symbol interference (ISI) causing channels to behave like transmission lines. Typical equalizer structures are digitally-controlled FIR filters that consume tens of milliwatts in power. This paper presents the design and simulation results of an active inductor equalizer for ground referenced signaling (GRS) receivers. Providing a tunable complex pole to the receiver transfer function allows for ISI cancellation with little power overhead. The proposed system equalizes at 25 Gb/s and consumes 470 μW. Compared to previous work, this system achieves a reduction in FOM between 48× and 218× in mW per Gb/s.

We present a design methodology for a nanoscale self-assembling fabrication process that uses the specificity of DNA hybridization to guide the formation of electrical circuitry. Custom design software allows us to specify the function of a structure in a way similar to that used by VLSI circuit designers. In an analogous manner to generating masks for a photolithographic process, our software generates an assembly procedure including DNA sequence allocation. We have found that the number of unique DNA sequences needed to assemble a structure scales with its surface area. Using a simple face-serial assembly order we can specify an unambiguous assembly sequence for a structure of any size with only 15 unique DNA sequences.

High-speed I/O circuits, once used only for PHYs, are now widely used for intra-system signaling as well because of their bandwidth, power, area, and cost advantages. This technology enables chips with over 1 Tb/s of I/O bandwidth today and over 10 Tb/s of bandwidth by 2010 as both signaling rates and number of high-speed I/Os increase with process scaling. Key technologies that enable this growth in I/O performance include low-jitter clock circuits and equalized signaling. An analysis of clock jitter and channel interference suggests that signaling rates should track transistor performance to rates of at least 40 Gb/s over boards, back-planes, and short-distance cables.

We describe PixelFlow, an architecture for high-speed image generation that overcomes the transformation-and frame-bufferaccess bottlenecks of conventional hardware rendering architectures.PixelFlow uses the technique of image composition: it distributes the rendering task over an array of identical renderers, each of which computes a fill-screen image of a fraction of the primitives.A high-performance image-composition network composites these images in real time to produce an image of the entire scene.Image-composition architectures offer performance that scales linearly with the number of renderers; there is no fundamental limit to the maximum performance achievable using this approach.A single PixelFlow renderer rasterizes up to 1.4 million triangles per second, and an n-renderer system can rasterize at up to n times this basic rate. PixelFlow performs antialiasing by supersampling.It supports defemed shading with separate hardware shaders that operate on composite images containing intermediate pixel data.PixelFlow shaders compute complex shading algorithms and procedural and image-based textures in real-time.The shading rate is independent of scene complexity.A Pixel Flow system can be coupled to a parallel supercomputer to serve as an immediatemode graphics server, or it can maintain a display list for retainedmode rendering.The PixelFlow design has been simulated extensively at high level.Custom chip design is underway.We anticipate a working system by late 1993.

This paper introduces the architecture and initial algorithms for Pixel-Planes 5, a heterogeneous multi-computer designed both for high-speed polygon and sphere rendering (1M Phong-shaded triangles/second) and for supporting algorithm and application research in interactive 3D graphics. Techniques are described for volume rendering at multiple frames per second, font generation directly from conic spline descriptions, and rapid calculation of radiosity form-factors. The hardware consists of up to 32 math-oriented processors, up to 16 rendering units, and a conventional 1280 × 1024-pixel frame buffer, interconnected by a 5 gigabit ring network. Each rendering unit consists of a 128 × 128-pixel array of processors-with-memory with parallel quadratic expression evaluation for every pixel. Implemented on 1.6 micron CMOS chips designed to run at 40MHz, this array has 208 bits/pixel on-chip and is connected to a video RAM memory system that provides 4,096 bits of off-chip memory. Rendering units can be independently reasigned to any part of the screen or to non-screen-oriented computation. As of April 1989, both hardware and software are still under construction, with initial system operation scheduled for fall 1989.

Pixel-planes is a logic-enhanced memory system for raster graphics and imaging. Although each pixel-memory is enhanced with a one-bit ALU, the system's real power comes from a tree of one-bit adders that can evaluate linear expressions Ax+By+C for every pixel (x,y) simultaneously, as fast as the ALUs and the memory circuits can accept the results. We and others have begun to develop a variety of algorithms that exploit this fast linear expression evaluation capability. In this paper we report some of those results. Illustrated in this paper is a sample image from a small working prototype of the Pixel-planes hardware and a variety of images from simulations of a full-scale system. Timing estimates indicate that 30,000 smooth shaded triangles can be generated per second, or 21,000 smooth-shaded and shadowed triangles can be generated per second, or over 25,000 shaded spheres can be generated per second. Image-enhancement by adaptive histogram equalization can be performed within 4 seconds on a 512x512 image.