This paper describes a new strategic information system planning methodology, called ISISP (integrated strategic information system planning), which combines both top- down and bottom-up methodologies for strategic information system planning. In ISISP, portfolio derived from CRUD matrix will union with portfolio derived from SWOT/strategic themes which results in three sets of applications, namely the existing non-core applications, the core applications and the future applications. Then application transformation is applied to both core and non core application groups. For the future application group, each application will be mapped onto the existing CRUD matrix resulting in a new CRUD matrix, called ICRUD, which represents the information architecture that bridges the existing applications to the future strategically derived mission critical applications. The ISISP methodology therefore facilitates the actual implementations since all application boundaries will be derivable for the ICRUD matrix. Also, the business areas will be focused and realistic. The resultant application portfolio would be more suitable for creating IT-enabled enterprise since both existing and future strategic applications are taken care for.

The authors present closed-form check-predicting equations for deriving Berger checks (J.M. Berger, 1961) for array multipliers and array dividers, respectively. Braun's array multipliers and Guild's array dividers are examined. Example check circuits are also presented.>

A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is presented. The fault and error models of a large class of VLSI ALU designs are discussed. The proposed design is proved to be fault-secure and self-testing with respect to any single fault in the ALU part. The proposed BCP ALU is proved to be SFS with any design of BCP circuit. Consequently, a self-checking processor whose data path is encoded entirely in a Berger code can be achieved. An efficient self-checking processor can then be designed.>

The authors present the design of an 11-transistor combinational NMOS 1-out-of-3 code checker. The checker is totally self-checking (TSC) with respect to 36 faults out of a total of 58 faults defined at the NMOS switch and layout geometrical levels, and achieves the TSC goal of a checker for most of the fault sequences. The minimum fault sequences under which the TSC goal is lost are composed of at least three faults. This might be considered as a sufficient level of safety for some implementations.>

A novel approach to designing concurrent-error-detecting arithmetic and logic units using Berger code is presented. Several theorems are developed on Berger check predictions for arithmetic and logical operations. Specifically, the Berger check prediction is proposed for additions and subtractions with unsigned numbers as well as signed numbers. Berger check prediction for 16 logical operations and shift operations, multiplication, and division are given. The proposed scheme may provide a considerable saving in the hardware logic (or chip area) in implementing a self-checking arithmetic logic unit (ALU) and may ultimately make feasible a single-chip self-checking microprocessor or reduced-instruction-set-computer (RISC) design.>

A new channel routing algorithm called DTR (Defect-Tolerant Routing) is investigated. This algorithm minimizes the total area and simultaneously maximizes the performance by reducing the critical area which can potentially be the source of logical faults caused by the bridging effects of spot defects. Experimental results show DTR produces less critical area than Yoshimura&Kuh's algorithm [1].

A ring-based media access control protocol and architecture, Fast Ring, which combines the best features of the token ring and contention ring, is proposed. For this protocol, a free token circulates on the ring when the ring is idle. A ready station can transmit either by capturing the token or sensing the ring idle. The protocol works in such a way that the ready node which captures the free token, before or while transmitting, is able to continue transmission. All the other contending nodes have to stop their transmissions and then send the abort signal when they receive the upstream transmission. After its transmission, the successful station puts a free token on the ring and the protocol enters the token mode. It behaves like the token ring protocol until the ring becomes idle again when all the ready nodes complete their transmissions. Comparison of the performance of Fast Ring with those of contention ring, token ring, and carrier-sense multiaccess with collision detection protocols shows that the Fast Ring outperforms all these local area network protocols over the whole throughput range at all transmission rates.>

A comparison is made between two tree data structures that support region queries for VLSI layout systems. In a previous study, J.B. Rosenberg (ibid., vol.CAD-4, no.1, p.53-67, 1985) demonstrated that four-dimensional trees have a faster speed but use more memory space than quad trees with bisector lists. In this study the authors show that quad trees without bisector lists, for some small threshold values, have a better speed and require less storage than four-dimensional trees.>

A protocol called linear conflict resolution (LCR) for unidirectional broadcast bus networks is introduced. This protocol is shown to be suitable for both LAN (local area network) and MAN (metropolitan area network) environments. LCR combines the benefits of the quick access of the Aloha protocol and the deterministic access of TDMA (time-division multiple access). Not only could the maximum throughput of LCR be increased to near 100% but also the network is stable in that the delay is finite for all the operating conditions. The channel capacity of the LCR protocol is less sensitive to the bus characteristics than most of the existing protocols. Numerical results indicate that LCR exhibits good performance over a wide range of network sizes.>

A class of modified single-state shuffle/exchange (S/E) networks with reconfigurable connections is described. The capability of these modified networks to simulate every arbitrary permutation and other multistage S/E networks is studied. In particular, the upper bounds on simulating six multistage S/E networks are given. It is also shown that C.L. Wu and T.Y. Feng's (1981) modified single-stage S/E network is optimal in terms of its universality and cost for the networks with one reconfigurable connection. However, some of the modified networks with two reconfigurable connections have better capability although they are slightly more expensive than Wu and Feng's network. Also proposed is a link folding scheme that can be used to reduce the connection complexity of implementing the connection selection mechanism.>

The use of shuffle/exchange (S/E) interconnection networks in multiprocessor systems has been proposed for several applications. In order to evaluate the potential performance and reliability of such systems, the effects of conflicts involving switch and memory contention should be determined. This paper presents a discrete Markov chain model to study the effects of such contention for S/E networks used in random access application environments. This model is used to derive memory bandwidth (MBW) of the system, with analytic expressions presented for 4 X 4 and 8 X 8 S/E networks. Two cases are considered. First, the model is applied to systems in which all processors issue their access requests synchronously, then this model is used to construct a traffic model which allows the generation of access requests at arbitrary times. The results of the analysis are compared with simulation results and the analytical results derived by Bhandarkar for the full Crossbar network. Besides the MBW, other interference-related parameters such as blocking probability, traffic, loading, and blocking delay are discussed. In particular, the loading effect of a 16 X 16 S/E network obtained from the model is compared with the results of the simulation from Wirsching's CONET model.