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Richard Absher

dblp:86/5888 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design
circuit partitioning
0.011989
Graph theoretic algorithms for the PLA folding problem · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation
logic synthesis
0.011989
Graph theoretic algorithms for the PLA folding problem · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation
physical design
0.011989
Graph theoretic algorithms for the PLA folding problem · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989
Electronic design automation › logic synthesis › logic optimization
PLA folding
0.011989
Graph theoretic algorithms for the PLA folding problem · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1989

Methods — techniques the papers use, named apart from their topics

greedy algorithm · 0.0clique detection · 0.0
YearPublicationVenuePosition
1991 Can Undergraduate Test Engineering Education Be "Faster, Better, Sooner?"
Richard Absher
ITC1
1989 Engineering Curricula for "Meeting the Tests of Time"
abstract
The authors describe a background study, course developments, and concepts for a curriculum in electronics test engineering. Their conclusion is that appropriate academic programs in electronics test engineering should be developed at the B.S., M.S., and Ph.D levels. The identification of the common background and education, as well as the implementation, of these programs requires strong university/industry cooperation and support. As exemplified by the present study, this process can occur at the local level. However, it is suggested that a broader input and a greater visibility are warranted, and it is recommenced that an organization such as the Test Technology Technical Committee coordinate the development of model curricula for 'meeting the tests of time'.>
Richard Absher, Ned Lecky
ITC1
1989 Graph theoretic algorithms for the PLA folding problem
abstract
Graph theoretic properties of the PLA folding problem which not only give insight into the various folding problems but also provide efficient algorithms for solving the problems are presented. This work is based on the transformation of the PLA into graphs where cliques (completely connected subgraphs) in the graphs correspond to PLA folding sets. A simple heuristic technique known as the greedy algorithm can often identify near-maximum cliques in polynomial time. Experimental data show that this technique is extremely effective when applied to the graphs which generally arise in folding. Variations of the general folding problem such as bipartite folding and constrained folding are addressed.>
Ned Lecky, O. J. Murphy, Richard Absher
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3