Demo Data from EDBT 2026 / reviewers in the wild / expert
Maria Sigala
dblp:86/6124
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 1983
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware reliability and fault tolerance · 57% Electronic design automation · 29% Integrated circuit design · 14% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance
self-checking circuits |
0.0 | 1 | 1983 | Fast and Efficient Totally Self-Checking Checkers for m-out-of-(2m ±1) Codes · IEEE Trans. Computers 1983 |
Hardware reliability and fault tolerance › self-checking circuits
totally self-checking checker |
0.0 | 1 | 1983 | Fast and Efficient Totally Self-Checking Checkers for m-out-of-(2m ±1) Codes · IEEE Trans. Computers 1983 |
Integrated circuit design
digital circuit design |
0.0 | 1 | 1978 | Polylinear Decomposition of Synchronous Sequential Machines · IEEE Trans. Computers 1978 |
Electronic design automation › logic synthesis › finite state machine synthesis
finite state machine decomposition |
0.0 | 1 | 1978 | Polylinear Decomposition of Synchronous Sequential Machines · IEEE Trans. Computers 1978 |
Electronic design automation › logic synthesis › logic optimization
state minimization |
0.0 | 1 | 1978 | Polylinear Decomposition of Synchronous Sequential Machines · IEEE Trans. Computers 1978 |
Methods — techniques the papers use, named apart from their topics
partitioning · 0.0logic design · 0.0substitution property · 0.0backward state transition function · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1983 | Error-Correcting Codes in Binary-Coded Radix-r ArithmetikabstractThis paper presents a new class of AN codes of high efficiency capable of correcting single errors in radix-r arithmetic with the binary coded digits—BCr—system. The errors corrected within a single radix-r digit are single errors of the binary digits with weight ±wi≤ r–1,i=1,2,···, m, which are used to encode the BCr digits. The corresponding arithmetic unit is made out of slices, one for each BCr digit. The AN codes considered have a generator A of the form A = τ·p where τ, p odd and rp=n-1 ≤ τk± 1. The criteria are applied to the BCD system, and we determine all τ < 100 and p < 200 for the most important BCD codes with weights ± wi < r –1, i = 1, 2, 3, 4. For each BCD code, the paper gives the numbers τ < 100 for which AN codes exist, and the maximum code efficiency E = 2·m·k/(A-1) attained at some p < 200. Constantin Halatsis, Nikolaos Gaitanis, Maria Sigala |
IEEE Trans. Computers | 3 |
| 1983 | Fast and Efficient Totally Self-Checking Checkers for m-out-of-(2m ±1) CodesabstractThis note is concerned with the design of fast totally self-checking checkers for m-out-of-(2m ± 1) codes. The new method uses only three levels of gates, and is based on the partitioning of the input lines into m blocks of two lines per block except for the last block. A first level of two-input AND and OR gates realizes the majority functions T(ki ≥ 1) and T(ki ≥ 2). These are combined through AND gates of a second level into the so-called product functions Pj1j2...jm, one for each class of input codewords that have jl, j2,···, jm 1's in the corresponding blocks of the input lines. Finally, two OR gates (third level) partition the product functions into two. The property of totally self-checking operation is achieved through the proper partitioning of the product functions into two classes. This note presents a systematic method of such partitioning. Also, the note determines the cost of these checkers and compares them to previous designs. Constantin Halatsis, Nikolaos Gaitanis, Maria Sigala |
IEEE Trans. Computers | 3 |
| 1978 | Polylinear Decomposition of Synchronous Sequential MachinesabstractThe paper presents systematic procedures for decomposing a sequential machine into submachines some or all of which are realized by polylinear sequential circuits. This polylinear decomposition is based upon classes of subsets of the set of states which possess the substitution property rather than upon partitions with substitution property. These classes are easily found using the backward state transition function of the machine and enables one to treat uniformly and simultaneously the problems of state minimization, machine decomposition in the classical or the polylinear way, finding the lattice of the partitions with substitution property, and periodic decomposition based upon classes that correspond to cyclic partitions. Procedures are developed for deriving optimal all polylinear decompositions and "good" partial polylinear decompositions of a machine. Constantin Halatsis, Maria Sigala, George Philokyprou |
IEEE Trans. Computers | 2 |