We describe a new linear programming (LP)-based hierarchical pitchmatching method. With a simplified treatment of the intercell constraints, the size of the LP problems is significantly reduced as compared to the best known results. In particular, the pitchmatching problem is decomposed into independent subproblems by exploiting the layout slicing structure. Each subproblem is further "folded" to reduce the LP problem size. We prove that the new method generates smaller LP problem than the previously best known approach. Experimental data show that the LP problem size can be 10 times smaller.>

We describe a new linear programming (LP)-based hierarchical pitchmatching method.Whh a simplified treatment of the intercell constraints, the size of the LP problems is significantly smaller than the best known methods.In particular, the pitchmatching problem is decomposed into independent subproblems by the natural slicing structure in layout.Each subproblem is folded further to reduce the LP problem size.Experiments show that the LP problem size can be 10 times smaller than the best known result.

New algorithms used in the GOALIE2 circuit extraction system are presented that are based on representing VLSI layout geometries as trapezoids. These include polygon-to-trapezoid decomposition, scanline management, and output sorting. The scanline algorithm virtually eliminates the redundant computation present in similar systems. It solves the VLSI layout analysis problem in O(n+k) expected time and O( square root n) expected space, where n is the total number of input segments and k is the total number of intersection points. The new scanline algorithm is robust in what it will maintain its performance over a wide range of layout styles. Experimental results show that the running time is O(n/sup 1.0547/), i.e. that these algorithms enable one to perform VLSI layout analysis in nearly linear time.>

An O(klog(k)+n) algorithm is developed, where n is the number of versions, to decompose rectilinear polygons into rectangles. This algorithm uses horizontal cuts only and reports nonoverlapping rectangles the union of which is the original rectilinear polygon. This algorithm has been programmed in Pascal on an Apollo DN320 workstation. Experimentation with rectilinear polygons from VLSI artwork indicate that the present algorithm is significantly faster than the plane sweep algorithm and the algorithm proposed by K.D. Gourley and D.M. Green (1983).>

We develop an efficient algorithm for net extraction. This algorithm is able to efficiently handle very large layouts even when memory is limited. This is done by effectively using disk storage. The algorithm has been programmed in Fortran and is superior to other existing net extractors.

We formulate a class of adaptive heuristics for combinatorial optimization. Recently proposed methods such as simulated annealing, probabilistic hill climbing, and sequence heuristics, as well as classical perturbation methods are all members of this class of adaptive heuristics. We expose the issues involved in using an adaptive heuristic in general, and simulated annealing, probabilistic hill climbing, and sequence heuristics in particular. These issues are investigated experimentally.

The performance of simulated annealing is compared to that of other Monte Carlo methods for optimization. Our experiments show that these other methods often perform better than simulated annealing.