Many communications systems like 3G and 4G-LTE require the fast Fourier transform (FFT) up to 4096 points, but applications such as synthetic aperture radar, frequency-modulated continuous-wave (FMCW) radar, and spectrum analyzers require much higher-order FFTs. This article addresses this demand by presenting an efficient architecture for high-throughput computation of large-scale FFTs, supporting sizes up to 32K points while also covering 4K, 8K, and 16K-point FFTs with coarse-grained flexibility. The design features a memory-based structure with 64 banks fully utilized by 32 radix-2 butterfly units (BFUs) to achieve a very high throughput. BFUs are built with a novel$m^{2}\text {acc}^{2}$unit that optimizes floating-point operations to gain more precision—that is, a better signal to quantization noise ratio (SQNR)—with approximately 20% less resources. An optimized addressing scheme, which dramatically reduces the amount of address signals to two 9-bit signals shared by all 64 memory banks without requiring any permutations or dynamic access methodologies, is complemented by a simple data controller to efficiently maximize throughput per clock cycle. A read-only memory (ROM)-based twiddle-factor generator supports the high data-rate demands of all BFUs without introducing latency. The architecture is validated on an FPGA and implemented as an ASIC in Global Foundries (GF)’ 22-nm FDSOI technology, achieving a throughput of 4.26 GS/s at 1 GHz for the 32K-point FFT. Compared to existing solutions, this design delivers a notable 45% improvement in normalized throughput per area, demonstrating its effectiveness for high-performance large-size FFT calculations.

Test and reliability are important aspects of high-quality chip manufacturing which can introduce a noticeable level of cost to the final silicon products. Hence, reducing the amount of required steps and even more significantly the correction actions during tests through self-calibration is valuable. This work proposes an auto power-up self-calibration technique for a Successive-Approximation (SAR) Analog to Digital Converter (ADC) in a 22nm FD-SOI CMOS Process. By removing the two most dominant error sources in the design during the power-up, only a quick single DC test is left to manufacturing process. The idea involves calibration of the two independent error sources one at a time and hence resulted in 9.53-bit ENOB performance at 4 times Nyquist bandwidth during extracted simulations. The back-gate of the FDSOI process devices were utilized as a tuning knob in the proposed calibration scheme without introducing any extra load in the signal path of the circuit.

This paper introduces an adaptive feedback calibration circuit designed for use in V2X (Vehicle-to-Everything) systems operating at 5.9 GHz within 5G NR systems. The adaptive loop comprises the observation receiver, functioning in the n47 frequency band (5855-5925 MHz), and the digital pre-distorter, both situated on the same die as the RF Power Amplifier. The TX signal, featuring a bandwidth of up to 40 MHz and a PAPR of 8 to 10 dB, undergoes digitization by a receiver with a notably high bandwidth, such as 120 MHz. Subsequently, the digitized signal is input into the digital pre-distortion circuit with a 10-bit high precision. Circuit characteristics obtained from post-layout simulations, as of the publication date, have been incorporated into a comprehensive model. Simulations assessing EVM and ACLR of the TX signal at the Front-end module output have been executed. The EVM value enhances from 5.2% RMS when the adaptive DPD is deactivated to 1.5% RMS when activated. Moreover, the ACLR decreases from -30 dBc to better than -40 dBc. The observation receiver of the calibration feedback system, designed using 130-nm SOI CMOS technology, possesses dimensions of 1750 μm $\times$ 3200 μm. The DPD circuit, situated on a separate die but utilizing the same process, features dimensions of 5980 μm $\times$ 6430 μm.

This paper presents a method that aims to reduce the complex cabling problem in robotics applications, so as to prevent difficulties in troubleshooting processes and failures in case of cable breaks. Examples in the literature have proven the reliability of the Bluetooth Low Energy (BLE) based communication systems and indicated that it could be employed in sensor data transfer applications. Therefore, our solution to the aforementioned issue is independent joint modules that comprise a motor driver, a microcontroller for running servo control loops, and a BLE device that enables the module to communicate with the main processor of the robot without the need of bulky cabling. Target applications for this method are mobile robots that encapsulate onboard processors and actuators that are deployed within a short range.

This paper presents a low cost wireless power transfer system tailored particularly for size limited insulation sealed wearable devices. The 5-V USB input system features a crystal oscillator as reference signal source, a class-E power stage, a transmit coil with tunable series resonance and a feedback path to tune the resonance for peak power transmission. Regardless of the receive coil, load, component variations or any external blockers, the system continuously targets peak power at the strict center frequency of 6.78 MHz for compliance with international frequency regulations. Design choices and experimental measurement results were presented along with detailed circuit diagrams. The design can transfer around 50mW power to a 15mm × 17mm × 1mm 40-turn receive coil in a charging pad area of as wide as 9cm × 9cm.

A two-stage differential-ramp based continuous-tuning IF VGA is introduced. The design has a bandwidth in excess of 100 MHz consuming 5-mA from a 1.2-V supply. The ramp generation circuit consumes additional 200 muA from a 2.5-V supply. Thanks to the multiple differential control ramps, 49-dB linear-in-dB continuous gain tuning range is achieved with 19-dBm OIP3 at the maximum gain setting. The input referred noise density of the proposed design at maximum gain setting of 40-dB is 3.5-nV/sqrt(Hz).

An all-digital symbol timing recovery technique that uses a 1-bit ADC, delay-XOR unit and a digital prefilter before the all-digital loop is analyzed. This approach provides a low-power, all-digital implementation in CMOS integrated circuit and exhibits very low jitter. The prefilter is arranged to eliminate frequency offsets on the input signal. The system is robust against fast and large Doppler shift and is therefore well suited for receivers in satellite applications. A symbol timing circuit based on this technique has been implemented for a wide range of bit rates (0.1-100 Kbps). It is synchronized within 3 or 4 bits in the presence of high carrier frequency offsets. A detailed performance study is carried out by both analytical simulation and hardware implementation to provide guidelines when the proposed scheme is applied to other transmission systems.

In this paper we present extremely flexible and low power digital binary ASK, PSK, and FSK demodulator architectures for short-range applications that use a limiter amplifier (i.e. high gain comparator) at the front-end. The limiter amplifier can be used at the front-end when the SNR of the received signal is high. This technique converts the analog signal to digital via one bit processing and eliminates mixers, PLL and AGC devices or replaces them with very low power digital counterparts. The rest of circuit is then implemented using digital signal processing (DSP) technique. Detailed system analysis of such demodulators are carried out in this paper. In addition, some new low-size and low-power modulators/demodulators are also described and analyzed for low-power short-range applications