This paper presents the design and the characterization in nanoscale CMOS technology of a Network Interface (NI) for on-chip communication infrastructure with hardware support of advanced networking functionalities: store & forward (S&F) transmission, error management, power management, ordering handling, security, QoS management, programmability, end-to-end protocol interoperability, remapping. The design has been conceived as a scalable architecture: The advanced features can be added on top of a basic NI core implementing data packetization and conversion of protocols, frequency and data size between the connected Intellectual Property (IP) core and the on chip network. The NI can be configured to reach the desired tradeoff between supported services and circuit complexity.

This paper presents a network emulator for rapid prototyping of SpaceWire Intellectual Property cores. SpaceWire is a fault-tolerant high-throughput standard widely used in space and avionic applications. Thanks to its inherent properties, SpaceWire can be effectively adopted for addressing dependability and bandwidth requirements of forthcoming active safety automotive applications. The proposed platform considers both anti-fuse and SRAM FPGA devices. A four-layer software stack ensures full control of prototype features, batch testing and ease of use.