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Eric Schell

dblp:86/835 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 62% Electronic design automation · 38%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design
combinational logic
0.011985
CADTOOLS: a CAD algorithm development system · DAC 1985
Electronic design automation › hardware verification and test
logic simulation
0.011985
CADTOOLS: a CAD algorithm development system · DAC 1985
Electronic design automation › hardware verification and test
testability analysis
0.011985
CADTOOLS: a CAD algorithm development system · DAC 1985

Methods — techniques the papers use, named apart from their topics

list handling · 0.0graph-oriented commands · 0.0
YearPublicationVenuePosition
1985 CADTOOLS: a CAD algorithm development system
abstract
This paper defines a development system for computer-aided design (CAD) algorithms for combinational logic networks. The principle features of this system include graph-oriented commands and control structures, list handling facilities, and an expandable library of commonly used CAD subprograms. Application programs written using the prototype system, CADTOOLS, include worst case path delay analysis, Sandia Controllability and Observability Analysis (SCOAP) testability measure, and logic simulation. The experience with these programs suggests that such a system can reduce the time required to develop CAD programs.
Eric Schell, M. Ray Mercer
DAC1