Hypergraphs are powerful mathematical structures that can model complex, high-order relationships in various domains, including social networks, bioinformatics, and recommender systems. However, generating realistic and diverse hypergraphs remains challenging due to their inherent complexity and lack of effective generative models. In this paper, we introduce a diffusion-based Hypergraph Generation (HYGENE) method that addresses these challenges through a progressive local expansion approach. HYGENE works on the bipartite representation of hypergraphs, starting with a single pair of connected nodes and iteratively expanding it to form the target hypergraph. At each step, nodes and hyperedges are added in a localized manner using a denoising diffusion process, which allows for the construction of the global structure before refining local details. Our experiments demonstrated the effectiveness of HYGENE, proving its ability to closely mimic a variety of properties in hypergraphs. To the best of our knowledge, this is the first attempt to employ diffusion models for hypergraph generation.

The diversity of Instruction Set Architectures (ISAs), each with its unique constraints and optimization strategies, presents significant opportunities and challenges in processor design. Modern processor vendors exploit these ISAs to enhance security, reliability, and performance. Recent security vulnerabilities, notably Spectre and Meltdown, have highlighted the critical need for robust hardware security measures. In this paper, we employ gem5, a state-of-the-art cycle-accurate simulation tool, to simulate the Spectre attack. We developed and modified scripts for both x86 and ARM architectures to ensure compatibility with gem5 version 23.1. Our simulation setup involved running attack scenarios under various configurations to gather comprehensive data on cache misses, cache hits, mispredicted branches, and level 2 cache hits and misses. In the simulation, we analyzed the trace files generated by gem5, utilizing a range of debug flags such as Exec for disassembly (dasm) insights. By detailed analysis of cache and branch prediction using detailed debug data revealed by gem5 traces, we identify some specific attack patterns that are useful for automating the detection of the attacks. Our future work aims to expand this analysis to include additional attack vectors and find more attack patterns, thereby strengthening our attack pattern recognition capabilities.

In this article, MinConvNets where the multiplications in the forward propagation path of CNNs are approximated by minimum comparator operations are introduced. Hardware complexity of minimum operator is of the order of O(N), whereas for multiplication it is O(N2). Firstly, a methodology to find approximate operations based on statistical correlation is presented. We show that it is possible to replace multipliers by minimum operations in the forward propagation under certain constraints, i.e. given similar mean and variances of the feature and the weight vectors. A modified training method which guarantees the above constraints is proposed. And it is shown that equivalent precision can be achieved during inference with MinConvNets by using transfer learning from well trained exact CNNs.

Magnetic tunnel junction (MTJ) is considered as a promising memory candidate in the more than Moore era because of high power efficiency, fast access speed, nearly infinite endurance and easy 3D integration. The nondeterministic switching behavior has been profited to exploit new directions for computing methods, such as stochastic computing. In this paper, the application of stochastic switching behavior in stochastic computing is explored for deep neural network (DNN). Stochastic computing method features low logic complexity, low energy consumption and fine-grained parallelism, boosting the performance of DNN system by combining MTJ. As a key block of stochastic computing, MTJ based true random number generator design is presented in details. The functionality has been validated by combining the hardware design and post-processing in software. Simulation results are demonstrated visibly by handwritten digits recognition test to show the accuracy. Furthermore, the performance is investigated in terms of accuracy, energy consumption and memory occupation to find more efficient techniques.

Reliability concerns arise in nonvolatile magnetoelectric random access memory (MeRAM) due to continuously nanotechnology scaling down and CMOS-magnetic hybrid integration. The primary objective of this work is to investigate failure mitigation in voltage-controlled magnetic anisotropy-magnetic tunnel junction (VCMA-MTJ) based 1T-1MTJ MeRAM bit-cell, by using MTJ compact model and 28nm fully depleted silicon on insulator (FD-SOI) process design-kit. A comprehensive reliability study is performed considering process variation and aging degradations, including hot carrier injection (HCI), bias temperature instability (BTI), soft breakdown (SBD) and radiation effect. Write assist techniques are proposed to ensure failure resilient MeRAM design. Bit line (BL) boost and negative source line (SL) methods show high efficiency in writing latency improvement and failure mitigation.

The energy scalability of ultra-low power nonvolatile (NV) large-scale integration (LSI) is explored in this paper. Multi-threshold computing (super/near/sub-$V_t$) in hybrid CMOS/ magnetic tunnel junction (MTJ) circuits are investigated based on SPICE-compatible MTJ model and fully depleted silicon on insulator (FD-SOI) devices. Ultra-low supply voltage operation bottlenecks associated with performance loss, parametric variations and function failure are studied in differential pair-based sensing circuit, MTJ writing/control circuit and other building blocks. A case study is performed with three typical NV-flip-flops (NV-FF), which are implemented with 28nm FD-SOI low $V_t$ (LVT) device and forward back-bias. Results show that MTJ writing/control circuit must operate at nominal supply (super-$V_t$) region to guarantee MTJ switching; sensing circuit is configured with near-$V_t$ operation (0.6V) with robustness consideration, whereas other parts could be implemented with near/sub-$V_t$ computing to achieve ultra-low power consumption and energy efficient operations.

This paper investigates the design architectures for reliable high-yield low operating voltage non-volatile flip-flops (NVFF) for zero-leakage and instantaneously-on ultra-low power applications in scaled CMOS technologies. A reliable thin-gate oxide NVFF, integrating OxRAM current-based storing and restoring solutions is designed and analyzed in 28nm FD-SOI. The proposed class of NVFF designs has been optimized for optimal OxRAM programming conditions that improve endurance and minimize programming power, while ensuring high yield. The OxRAM device silicon measurements show that a low programming current benefits endurance, but at the expense of a reduced memory window (ROFF/RON). Statistical analysis demonstrates that a low NVFF operating voltage in restore mode can be achieved with a narrow memory window by using the current-based restoring. In a representative design, compared to a standard FF, the non-volatility is added at the cost of less than 3% of performance and up to 3.5%-13% of active energy increase, with 108 cycles of endurance. Then compared with the data-retention FF supplied at 0.5V, NVFF reduces the sleep power consumption for standby modes longer than 0.34s for uniform Q switching (0.17s-0.6s) Finally, the low variability of the FD-SOI technology enables 3 sigma yield restore down to 0.7V.

Shadow-scan solutions are proposed in order to facilitate the implementation of faster scan flip-flops (FFs) with optional support for in-situ slack-time monitoring. These solutions can be applied to system FFs placed at the end of timing-critical paths while standard-scan cells are deployed in the rest of the system. Automated scan stitching and automated test pattern generation (ATPG) can be performed transparently with commercial tools. The generated test patterns cover not only the mission logic but also the monitoring infrastructure. The latency of itc'99 benchmark circuits could be reduced with up to 10% while the stuck-at fault coverage (FC) was preserved as compared to circuit versions with full standard-scan design. Limited variations in the number of test patterns were observed when support for in-situ slack-time monitoring was provided.

As CMOS technology enters the nanometer regime, manufacturing defects are becoming a challenging concern in current and future technologies. This work aims at improving defect tolerance in FPGAs which are certainly affected by technology downsizing. Since the cornerstone of the FPGA logic and interconnect resources is the multiplexer, we compare different hardened architectures of the multiplexer in terms of robustness, area, power and delay, in order to select the most convenient one according to a design metric we define. The architectures are studied under single defect injection by a tool that models several possible defects for a given design according to its extracted netlist. Eventually, the robustness gain using the chosen multiplexer is assessed for different sizes of FPGA look-up tables.

This paper proposes a modified hybrid method for the reliability assessment of digital circuits. Such method deals naturally with the occurrence of multiple faults while taking logic masking into account. An extension of the method is proposed so that sequential logic is also supported. The results show that it is in good agreement with other methods in the literature.

In-situ slack-time monitoring may be used to enable ambitious power management policies under circuit wear-out and dynamic temperature and supply voltage variations. Given a limited hardware budget, it becomes crucial to be able to select the most appropriate places for in-situ slack-time monitoring. Here, two metrics are proposed to guide the selection of a set of flip-flops (FFs) for in-situ slack-time monitoring. The goal of these metrics is to maximize the ratio of clock cycles with at least one monitor activated and the number of activated monitors per clock cycle. The activation probability of a monitor is evaluated with the help of timing simulations as the probability that signals are propagated along the monitored timing-critical paths. It is shown that in-situ slack-time monitors with detection windows correlated to the minimum slack-time of the monitored timing-critical paths can provide better results than similar monitors with a constant detection window for the same impact on the circuit latency.

This paper presents new scan solutions with low latency overhead and on-line monitoring support. Shadow flip-flops with scan design are associated to system flip-flops in order to (a) provide concurrent delay fault detection and (b) avoid the scan chain insertion of system flip-flops. A mixed scan architecture is proposed which involves flip-flops with shadow scan design at the end of timing-critical paths and flip-flops with standard scan at non-critical locations. In order to preserve system controllability during test, system flip-flops with shadow scan can be set in scan mode and selectively reset before switching to capture mode. It is shown that shadow scan design with asynchronous set and reset may have a lower latency overhead than standard scan design. A shadow scan solution is proposed which, in addition to concurrent delay fault detection, provides simultaneous scan and capture capability.

In this paper, we propose the implementation of multiple defect-tolerant techniques on an SRAM-based FPGA. These techniques include redundancy at both the logic block and intra-cluster interconnect. In the logic block, redundancy is implemented at the multiplexer level. Its efficiency is analyzed by injecting a single defect at the output of a multiplexer, considering all possible locations and input combinations. While at the interconnect level, fine grain redundancy is introduced which not only bypasses defects but also increases routability. Taking advantage of the sparse intra-cluster interconnect structures, routability is further improved by efficient distribution of feedback paths allowing more flexibility in the connections among logic blocks. Emulation results show a significant improvement of about 15% and 34% in the robustness of logic block and intra-cluster interconnect respectively. Furthermore, the impact of these hardening schemes on the testability of the FPGA cluster for manufacturing defects is also investigated in terms of maximum achievable fault coverage and the respective cost.

This paper proposes a method to analyze the effect of manufacturing defects and soft errors: stuck-ats and bit flips, on a cluster in a Mesh FPGA architecture. The cluster reliability is evaluated with a technique that is used in case of either a single error or multiple simultaneous faults. Simulation results show that the cluster is more robust to stuck-ats than to bit-flips, whatever the configuration memory is. Then, for selective hardening against bit flips, we propose an approach to identify the critical path and the most eligible component that is likely to improve the cluster reliability.

We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of combinatorial logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.

Digital processing in Time Interleaved High-Pass Sigma-Delta (TIHPSigmaDelta) Analog to Digital Converter (ADC) remains a bottleneck to realize high performances data converters. This paper proposes a new digital filter architecture which use comb-filter cells. Comparing to existing solutions, our circuit reduces considerably complexity and power consumption of the digital post-filtering at the back end of the TIHPSigmaDelta. The proposed solution was validated and synthesized in a 1.2 V, 65 nm CMOS process using VHDL language. For a clock rate of 220 MHz, the evaluated power consumption and die area are 12 muW and 0.13 mm2respectively.

In this paper a reconfigurable implementation for the data detection in high data rate direct sequence code division multiple access (DS-CDMA) connections is presented. Due to some well defined real time system parameters, traditional implementations of this detector which deal with the mean operational case are not optimal. They consume a lot of power in the favorable operational cases and they loose a diversity gain in the worst cases. Thanks to reconfigurability, a detector can adapt its configuration to each operational condition. Reconfigurability can perform jointly performance and computational power optimization. Implementation issues have shown that the traditional DSPs provide a high degree of flexibility but they are inefficient for the high rate processing constraints involved to DS-CDMA detection with low spreading factors (SF). A reconfigurable hardware implementation is proposed and analyzed which besides its performance capabilities provides a minimum area overhead.

Recent advances in the reconfigurability concept have now made it possible to design blocks of the transceiver chain which can change its functionality in real time. Reconfigurability in general can provide performance improvements and reduction of the battery power consumption. In this paper we focus on the well-known Rake principle and we propose a reconfigurable receiver structure, able to support the required processing for a RAKE combination and a one-stage inter-path interference canceller (IC). This approach allows a more efficient use of the constraint calculation power of the reception block and improves the system performance. Through theoretical analysis and simulation, we also investigate a controller which can supervise, at run-time, switching between the two possible configurations.

Algebraic-geometry (AG) family of codes contains sequences with excellent asymptotic behaviour, but only few pieces of work have treated their hardware implementation. In this paper, we investigate an algorithm for decoding AG codes from the hardware feasibility point of view. We modify the original strategy in order to obtain a new structure more suitable for hardware implementation.

In this work, we deal with the design and implementation of a decimation filter to be used in wideband radio-frequency receiver. The paper outlines architecture considerations for multistandard wireless transceivers. Also, it describes the design steps and the tradeoffs concerning the hardware implementation. GSM and DECT standards specifications are met by the proposed filtering cascade structure. The filter processes six-bit data stream input from a fourth-order sigma-delta modulator and has been prototyped in a field-programmable gate array device.

Base-band building blocks are critical components in radio receivers based on direct conversion architectures. Homodyne receivers can perform digital channel filtering, thus allowing a simple multi-standard channel selection implementation. The drawback of this scheme is the severe ADC requirements on dynamic range and linearity. In spite of this, those requirements can be relaxed if the antialiasing filter attenuates significantly in-band interferers. This paper presents a method that allows one to find a double trade-off between: filter complexity and converter complexity, ADC linearity and ADC resolution, verified for GSM, DECT and UMTS standards.

No abstract available.