EDBT 2026 Demo / reviewers in the wild / expert
Kai-Hsiang Chang
dblp:86/9299
· DBLP profile ↗
6ranked-venue papers
0as first author
2since 2021 · last 2026
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 2 since 2021Graphics, computer vision, multimedia, augmented reality and games · 2Artificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Artificial intelligence
1 paper |
Face, body and person analysis · 50% Kernel, tree and ensemble methods · 25% Image recognition and object detection · 25% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Computer vision › Image recognition and object detection › object detection
coarse-to-fine detection |
0.2 | 1 | 2015 | Regressive Tree Structured Model for Facial Landmark Localization · ICCV 2015 |
Computer vision › Face, body and person analysis
face alignment |
0.2 | 1 | 2015 | Regressive Tree Structured Model for Facial Landmark Localization · ICCV 2015 |
Computer vision › Face, body and person analysis
face detection |
0.2 | 1 | 2015 | Regressive Tree Structured Model for Facial Landmark Localization · ICCV 2015 |
Machine learning › Kernel, tree and ensemble methods
tree-based models |
0.2 | 1 | 2015 | Regressive Tree Structured Model for Facial Landmark Localization · ICCV 2015 |
Methods — techniques the papers use, named apart from their topics
tree-structured model · 0.2support vector regression · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | An Effective Built-In Self-Test Scheme for Digital Computing-In Memories with MAC Function
Wen-Ching Liao, Kai-Hsiang Chang, Jin-Fu Li 0001 |
VTS | 2 |
| 2025 | All-Digital CMOS Pulse-Shrinking Time-to-Digital Converter With Built-in Offset-Error Cancellation and Smart Temperature SensorabstractThis brief presents an all-digital CMOS time-to-digital converter (TDC) with an integrated smart temperature sensor (STS), effectively reducing circuit complexity and cost. Unlike previous designs employing a single coupling unit, the proposed TDC adopts a two-coupling-unit structure, simplifying the overall architecture while enabling pulse-shrinking time measurement and offset-error cancellation within a single cyclic delay line. The built-in cancellation enhances linearity while minimizing overhead. Notably, the integrated STS requires only one additional coupling unit, ensuring a negligible impact on circuit complexity and cost. Fabricated using the TSMC 0.35-$\mu $m CMOS process, the proposed design demonstrates improved cost efficiency compared to prior works. Experimental results validate the successful measurement of time and temperature, highlighting the advantages of reduced complexity and cost savings. Chun-Chi Chen, Chao-Lieh Chen, Kai-Hsiang Chang |
IEEE Trans. Very Large Scale Integr. Syst. | 3 |
| 2020 | All-Digital Cost-Efficient CMOS Digital-to-Time Converter Using Binary-Weighted Pulse ExpansionabstractThis brief presents a cost-efficient all-digital CMOS digital-to-time converter (DTC) that innovatively applies binary-weighted pulse expansion. The DTC consists of a pulse generator (PG) for pulse generation (tp), a binary-weighted pulse-expanding circuit (BWPEC) as a main circuit for digital-to-time conversion, and a time subtractor (TS) for tpremoval. Compared with the original pulse-expanding unit (PEU), a novel PEU with reduced complexity and a linear pulse expansion was developed for binary-weighted operation. The use of the BWPEC with the binary-weighted PEUs exhibits lower circuit complexity and considerably reduces the circuit cost compared to the original unary-weighted pulse-expanding circuit (PEC). A prototype of the 4-bit all-digital DTC was fabricated using a Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-μm CMOS process. The fabricated DTC exhibited an area of 0.02 mm2achieving twofold improvement considerably. The measured resolution was approximately 5 ps, with the integral nonlinearity being -1.2-1 least significant bit (LSB). Without requiring an advanced CMOS process, the pulse variation technique with a simple structure can easily achieve fine resolution. The DTC features cost-efficient pulse expansion with binary weights and low circuit complexity. Chun-Chi Chen, Chorng-Sii Hwang, Kai-Hsiang Chang |
IEEE Trans. Very Large Scale Integr. Syst. | 3 |
| 2015 | Regressive Tree Structured Model for Facial Landmark LocalizationabstractAlthough the Tree Structured Model (TSM) is proven effective for solving face detection, pose estimation and landmark localization in an unified model, its sluggish run time makes it unfavorable in practical applications, especially when dealing with cases of multiple faces. We propose the Regressive Tree Structure Model (RTSM) to improve the run-time speed and localization accuracy. The RTSM is composed of two component TSMs, the coarse TSM (c-TSM) and the refined TSM (r-TSM), and a Bilateral Support Vector Regressor (BSVR). The c-TSM is built on the low-resolution octaves of samples so that it provides coarse but fast face detection. The r-TSM is built on the mid-resolution octaves so that it can locate the landmarks on the face candidates given by the c-TSM and improve precision. The r-TSM based landmarks are used in the forward BSVR as references to locate the dense set of landmarks, which are then used in the backward BSVR to relocate the landmarks with large localization errors. The forward and backward regression goes on iteratively until convergence. The performance of the RTSM is validated on three benchmark databases, the Multi-PIE, LFPW and AFW, and compared with the latest TSM to demonstrate its efficacy. Gee-Sern Hsu, Kai-Hsiang Chang, Shih-Chieh Huang |
ICCV | 2 |
| 2015 | Face detection and landmark localization using Bilayer Tree Structured ModelabstractAlthough the Tree Structured Model (TSM) is proven effective for face detection, pose estimation and landmark localization, its sluggish runtime makes it unfavorable in practical applications. We propose the Bilayer Tree Structure Model (BTSM) to improve the run-time speed while keeping the performance unchanged or slightly better. The BTSM is composed of two component TSMs, the coarse c-TSM and the refined r-TSM. The c-TSM is trained on low-resolution samples so that it can provide coarse but fast detection, The r-TSM is trained on mid-resolution samples so that it can locate precise part locations. The performance of the BTSM is validated on three benchmark databases, the Multi-PIE, LFPW and AFW, and compared with the latest TSM to demonstrate its efficacy. Gee-Sern Hsu, Kai-Hsiang Chang, Shih-Chieh Huang, Sheng-Luen Chung |
ICIP | 2 |
| 2011 | Evolving a Test Oracle in Black-Box Testing
Farn Wang, Jung-Hsuan Wu, Chung-Hao Huang, Kai-Hsiang Chang |
FASE | 4 |