One of the challenges of designing for coarse-grain reconfigurable arrays is the need for mature tools. This is especially important because of the heterogeneity of the larger, more predefined (and hence more specialized) array elements. This work describes the use of a genetic algorithm (GA) to automate the physical binding phase of kernel design. We identify the generalizable features of an example platform and discuss suitable ways to harness the binding problem to a GA search engine.

Dynamic logic is an alternative way of making logic circuit cells and numerous techniques have been developed to take advantage of its unique characteristics. Particularly, techniques such as the true-single-phase-clock (TSPC) have been used very successfully for fast and low-power applications. However one cannot synthesize dynamic logic gates with the same ease as static gates. One reason is there are no simple rules to connect the many circuit types of dynamic gates to static gates. This paper addresses the problem of finding connection rules for a given set of gate types. The fundamental cell circuit types for dynamic logic gates are analyzed first together with static logic gates. A common set of principles of operation and connections is then identified and later applied to discover which are the feasible connections between cell circuit types identified.

Selecting a clock period is an essential step in implementing hardware from behavioral descriptions. Current methods either estimate the clock prior to scheduling or involve exhaustive runs of the high-level synthesis tools to obtain a globally optimum clock period. Further, the potential benefits of allowing the use of multiple clocks for performance optimization has not been investigated. This paper presents a clock selection method that works simultaneously with synthesis by selecting a clock from an optimal clock set. The synthesis is iterative and is optimized by evolutionary techniques. The method is very flexible and can accommodate a large set of potentially optimal clocks. We also present multirate clock synthesis with path-dependent clock selection where different paths in a control data flow graph (CDFG) are optimized with different clock periods. The results shown prove the method's effectiveness.

This paper presents a methodology and tool (Power-Profiler) for the optimization of average and peak power consumption in the behavioral synthesis of ASICs.It considers lowering operating voltages, disabling the clock of components not in use, and architectural trade-offs, while also keeping silicon area at reasonable sizes.By attacking the power problem from the behavioral level, it can exploit an application's inherent parallelism to meet the desired performance and compensate for slower and less power-hungry operators.

New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques by making use of a global priority function. A new design-space exploration technique, which combines this algorithm with an existing one based on time constraints, is also presented.

A general scheduling methodology is presented that can be integrated into specialized or general-purpose high-level synthesis systems. An initial version of the force-directed scheduling algorithm at the heart of this methodology was originally presented by the authors in 1987. The latest implementation of the logarithm introduced here reduces the number of functional units, storage units, and buses required by balancing the concurrency of operations assigned to them. The algorithm supports a comprehensive set of constraint types and scheduling modes. These include multicycle and chained operations; mutually exclusive operations; scheduling under fixed global timing constraints with minimization of functional unit costs, minimization of register costs, and minimization of global interconnect requirements; scheduling with local time constraints (on operation pairs); scheduling under fixed hardware resource constraints; functional pipelining; and structural pipeline (use of pipeline functional units). Examples from current literature, one of which was chosen as a benchmark for the 1988 High-Level Synthesis Workshop, are used to illustrate the effectiveness of the approach.>

The HAL system performs data path synthesis using a new scheduling algorithm that is part of an interdependent scheduling and allocation scheme. This scheme uses an estimate of the hardware allocation to guide and optimize the scheduling subtask. The allocation information includes the number, type, speed and cost of hardware modules as well as the associated multiplexer and interconnect costs.

A novel approach to automatic data path synthesis is presented. This approach features innovations in the synthesis process as well as in the system implementation.

The requirements of an algorithmic level hardware description language can be met by a software language with only limited feature enhancement. This paper discusses the feasibility of using a subset of Ada as a hardware description language. Methods are presented for realizing the extra features required for hardware description within the syntax of Ada. This allows the compiled Ada program to act as a functional simulator. Our particular context for hardware description is as a source language for a hardware compiler. Rules are presented for translating a circuit described in the Ada subset onto a control/data-flow graph (CDFG), our intermediate level form.