A new parallel distributed algorithm for Golomb (1977) ruler derivation is presented. This algorithm was used to prove computationally the optimality of three rulers. Two of these were previously proven but yet unpublished, and the authors' independent derivation confirmed these results. The last ruler, of 19 marks and size 246, was known to be near-optimal and was computationally proven optimal in this work.

This paper describes the latest generation of pin electronics developed for a high-speed verification ATE system. The pin electronics sub-system provides a driverireceiver with outstanding bandwidth in addition to per-pin current loading and per-pin parametrics. A f.11 custom GaAs IC provides the major features and advanced performance of the driver, receiver, and current load. The combined modules use only 2.5 square inches of circuit board area per tester channel. This paper details the circuit design and measured perfor,mance of the GaAs IC and the three hybrid multichip rzwdules that complete the pin electronics Bnctions.