A Printed Circuit Board (PCB) provides the backbone for the interconnection of diverse electronic components into an electronic system. Unfortunately, the increased use of untrusted third-party PCB design/fabrication facilities and the long, distributed, supply chain of a PCB makes it extremely vulnerable to variety of integrity violation attacks, primarily different forms of counterfeiting, including cloning and recycling. In this paper, we propose a novel low-overhead and robust method to authenticate PCBs that utilizes an existing industry standard - IEEE 1149.1 or JTAG test infrastructure to extract high-quality signatures with high entropy. Since the signature encapsulates the intrinsic properties of the PCB components, it can be effectively used to identify malicious modifications of PCB components (e.g. replacing a chip) in a supply chain or during field operation. Measurement results with 30 custom fabricated test boards are promising in terms of uniqueness (48.34% inter-PCB hamming distance) and robustness (1.22% intra-PCB Hamming Distance) of 128-bit authentication signature.

Counterfeit chips in the supply chain as well as hardware Trojan (HT) attacks pose serious threats to the semiconductor industry. If undetected before deployment, they can lead to serious consequences including system performance/reliability issues during field operation and potential revenue/reputation loss for a trusted manufacturer. Currently, no unified detection method is available that can simultaneously address these integrity violations in integrated circuits (ICs). In addition, most existing detection approaches require a set of golden chips as a reference, which significantly increases the test cost and complexity. Furthermore, in some scenarios, it may be extremely difficult to obtain golden chips. In this paper, we present a novel unified IC integrity analysis approach that can effectively detect both recycled counterfeit ICs (the most dominant form of counterfeiting) as well as Trojan attacks in ICs without the need of golden chips. The proposed approach, referred to as self-similarity-based microchip integrity analysis (SeMIA), exploits intrinsic structural self-similarity in a design (e.g., multiple cores, multiple functional units of the same type, different parts of an adder) to isolate recycled chips and HT attacks under large inter- and intra-die process variations. It compares dynamic current (${I} _{\text {DDT}}$) signatures between two adjacent similar circuit structures using an appropriate isolation metric to detect such attacks with high degree of confidence. SeMIA does not rely on any embedded structure for authentication, thus it comes at virtually zero hardware overhead and can be applied to chips already produced. Through extensive simulations, we show that for 15% inter- and 10% intra-die variations in threshold voltage for a 45 nm CMOS process, over 98% of recycled chips can be reliably identified. Finally, experimental measurements on field programmable gate array chips demonstrate effectiveness of SeMIA for protection against both attacks.

Physical unclonable function (PUF) has emerged as an attractive primitive to address diverse hardware security issues in integrated circuits, such as authentication and cryptographic key generation. Most of the existing PUFs rely on dedicated circuit structure for generating random signatures. It often causes concerns due to extra design efforts and hardware overhead. Moreover, the hardware complexity increases with higher entropy requirement, which may be unacceptable in area-constrained applications. In this paper, we propose DScanPUF, a novel PUF structure that leverages on the scan chain, a prevalent design-for-test structure in a chip. It is based on a low-overhead delay measurement structure consisting of a phase-locked loop and multiple clock delay lines to measure scan path delays at high resolution. A method is proposed to transform the responses into robust binary signatures. We note that the area of DScanPUF is only 18% of the ring-oscillator (RO) PUF with 1024 ROs. Moreover, it can be easily integrated into a design without any influence on testability. DScanPUF is evaluated with test results from 31 field-programmable gate array chips, which show good randomness, uniqueness and reproducibility under temperature, and supply voltage fluctuations. We also show that the signature is robust under aging effects on scan paths through a simulation at 45-nm CMOS process. Finally, we propose a simple structural modification to further improve the signature robustness.

Security is becoming an increasingly important parameter in current system-on-chip (SoC) design due to diverse hardware security attacks that can affect manufacturers, system designers or end users. To effectively address the security issues, design-time considerations, e.g. incorporation of design-for-security (DfS) features, are becoming essential. However, DfS measures for diverse security threats require specific design modifications to achieve target security level, which significantly increases design effort thus time-to-market, and usually incurs considerable design overhead. In addition, the general heterogeneous architecture of current SoCs makes many core-level DfS mechanisms unusable at SoC level. In this paper, we propose a centralized on-chip infrastructure IP for SoC security (IIPS), which alleviates the SoC designers from separately addressing different security issues through design modifications in multiple cores. It also provides ease of integration and functional scalability. We consider a specific implementation of IIPS that provides protection against: (1) scan-based attack for information leakage through low-overhead authentication; (2) counterfeiting attacks through integration of a Physical Unclonable Function (PUF); and (3) hardware Trojan attacks through a test infrastructure fortrust validation. To make the IP amenable for plug-and-play during SoC design, working protocols of the security functions are designed to comply with IEEE 1500 Standard for Embedded Core Test (SECT). Since IIPS resides outside the functional modules, it does not incur functional performance or power overhead. Simulations and experiments on example SoC designs validate the effectiveness of IIPS in providing protections against diverse attacks at a low hardware overhead.

Counterfeit chips in a supply chain have emerged as a major security concern in the semiconductor industry with serious potential consequences (such as performance degradation, revenue, and reputation loss). With rising incidences of this attack, wide-spread effort has been made in both industry and academia to develop effective countermeasures. However, existing solutions to protect against these attacks suffer from both robustness issue (in terms of detecting chips with minor functional/structural deviations) as well as design/area overhead and test cost. In addition, they cannot reliably detect different forms of cloning attacks. In this paper, we propose a novel characterization method to identify counterfeit chips - in particular, the cloned ones - based on extraction of scan path delay signatures of a chip. It uses the scan chain, a prevalent design-for-testability structure, to create a robust authentication signature. The proposed approach has two major advantages: 1) it comes at virtually zero design and hardware overhead, since it does not require any additional embedded structure; and 2) it alleviates the design house from characterizing each manufactured chip instance, thus mitigating test cost. In addition, a novel and practical method based on clock phase sweep is proposed to measure delay of short scan paths with high resolution. Using Monte Carlo simulation on the layouts of two ISCAS-89 benchmarks at 45-nm CMOS process, we observe that over 99% of counterfeit chips can be reliably identified even under large process variations. Effectiveness of the approach is also validated with delay measurements in field programmable gate array chips.

Rising incidences of counterfeit chips in the supply chain have posed a serious threat to the semiconductor industry. Recycling of used chips constitutes a major form of counterfeiting attacks. If undetected, they can lead to serious consequences including system performance/reliability issues during field operation and potential revenue/reputation loss for a trusted manufacturer. Existing validation approaches based on path delay analysis suffer from reduced robustness and sensitivity under large process variations. On the other hand, existing design solutions based on aging sensors require additional design/verification efforts and cannot be applied to legacy chips. In this paper, we present a novel recycled chip identification approach, CACI, that exploits differential aging in self-similar modules (e.g., different parts of an adder) to isolate aged chips under large inter- and intra-die process variations. It compares dynamic current (IDDT) signatures between two adjacent similar circuit structures in a chip. We derive an isolation metric based on multiple current comparisons to provide high level of confidence. CACI does not rely on any embedded structures for authentication, thus it comes at virtually zero design overhead and can be applied to chips already in the market. Through extensive simulations, we show that for 15% inter- and 10% intra-die variations in threshold voltage for a 45nm CMOS process, over 97% of recycled chips can be reliably identified.

The rapidly rising incidences of counterfeit Integrated Circuits (ICs) in the semiconductor supply chain pose a significant threat to the electronic industry. These ICs may suffer from functional, performance or reliability issues and can affect design houses, chip manufacturers, system designers as well as end users. The standard chip/package/system level tests are often inadequate in detecting various forms of counterfeit ICs. On the other hand, design approaches that enable IC authentication are often not attractive due to significant design effort, hardware overhead and test cost. In this paper, we propose a novel defense against counterfeiting attacks through a “chip locking approach”, where an IC is made non-operational by locking select pins through insertion of Antifuse (AF) devices in input/output circuitry. It can be unlocked through application of a hard-to-clone key. The key is internally stored in a onetime programmable non-volatile memory. The key storage and comparison circuit is protected against reverse engineering and side-channel analysis attacks. Through mathematical analysis and simulation results, we demonstrate that the proposed mechanism provides high level of protection against all major forms of counterfeiting attacks (reselling, remarking and cloning) at ultralow overhead (<; 0.01% area).

Physical Unclonable Functions (PUFs) have emerged as an attractive primitive to address diverse hardware security issues, such as chip authentication, intellectual property (IP) protection and cryptographic key generation. Existing PUFs, typically acquired and integrated in a design as a commodity, often incur considerable hardware overhead. Many of these PUFs also suffer from insufficient challenge-response pairs. In this paper, we propose ScanPUF, a novel PUF implementation using a common on-chip structure used for improving circuit testability, namely scan chain. It exploits path delay variations between the scan flip-flops in a scan chain to create high-quality (in terms of uniqueness and robustness) secret keys. Furthermore, since a scan chain provides large pool of scan paths to create a signature, we can achieve high volume of secret keys from each chip. Since it uses a prevalent on-chip structure, the overhead is extremely small (2.3% area of the RO-PUF), primarily contributed by small additional logic in the signature-generation cycle controller. Circuit-level simulation results with 1000 chips under inter- and intra-die process variations show high uniqueness of 49.9% average inter-die Hamming distance and good reproducibility of 5% intra-die Hamming distance below 85 °C. The temporal variations due to device aging effect e.g. bias temperature instability (BTI) lead to only 4% unstable bits for ten-year usage. The experimental evaluation on FPGA (Altera Cyclone-III) exhibits 47.1% average inter-Hamming distance, as well as 3.2% unstable bits at room temperature.

Side-channel attack (SCA) is a method in which an attacker aims at extracting secret information from crypto chips by analyzing physical parameters (e.g. power). SCA has emerged as a serious threat to many mathematically unbreakable cryptography systems. From an attacker's point of view, the difficulty of mounting SCA largely depends on Signal-to-Noise Ratio (SNR) of the side-channel information. It has been shown that SNR primarily depends on algorithmic and circuit-level implementation, measurement noise, as well as device thermal noise. However, to the best of our knowledge, there has not been any study on the effect of power delivery network (PDN) on SCA resistance. We note that the PDN plays a significant role in SNR of measured supply current. Furthermore, SCA resistance strongly depends on the operating frequency due to RLC structure of a power grid. In this paper, we analyze the effect of power grid on SCA and provide quantitative results to demonstrate the frequency-dependent SCA resistance due to PDN-induced noise. This property can potentially be exploited by an attacker to facilitate the attack by operating a device at favorable frequency points. On the other hand, from a designer's perspective, one can explore countermeasures to secure the device at all operating frequencies while minimizing the design overhead. Based on this observation, we propose a frequency-dependent noise-injection based compensation technique to efficiently protect against SCA. Simulation results using realistic PDN model as well as experimental measurements using FPGA test board validate the observations on role of PDN in SCA and the efficacy of the proposed compensation approach.

Physical Unclonable Functions (PUFs) have emerged as an attractive primitive to address diverse hardware security issues in Integrated Circuits (ICs). A majority of existing PUFs rely on a dedicated circuit structure for generating chip-specific signatures, which often imposes concerns due to area/power overhead and extra design efforts. Furthermore, existing PUF-based signature generation cannot be employed to authenticate chips already in the market. In this paper, we propose RESP, a novel PUF structure realized in embedded SRAM array, a prevalent component in processors and system-on-chips (SOCs), with virtually no design modification. RESP leverages on voltage-depend memory access failures (during write) to produce large volume of high-quality challenge-response pairs. Since many modern ICs integrate SRAM array of varying size with isolated power grid, RESP can be easily retrofitted into these chips. Circuit-level simulation of 1000 chips using realistic process variation model shows high uniqueness of 49.2% average inter-die Hamming distance and good reproducibility of 2.88% intra-die Hamming distance under temperature < 85°C. The device aging effect, e.g. bias temperature instability (BTI), results in only 4.95% estimated unstable bits for ten-year usage.

Algebraic soft-decision (ASD) decoding algorithm of Reed-Solomon (RS) codes can achieve better performance-complexity tradeoff than other soft-decision decoding algorithms. The interpolation is a major step of ASD algorithms. In the case that multiple test vectors are involved, the interpolation needs to be carried out for each vector and leads to very high hardware complexity. To enable the sharing of computation results in the interpolation for different vectors, a backward interpolation scheme was developed previously to eliminate points from a given interpolation result, which is a Grobner basis. However, this scheme can only eliminate all points in the same code position when their multiplicities are all one and the number of points is one less than the number of polynomials in the Grobner basis. Larger multiplicities are required to achieve better error-correcting performance. Moreover, for general ASD algorithms, the points in the same code position may have different multiplicities. In this paper, a generalized backward interpolation algorithm is proposed through constructing equivalent Grobner basis. It is capable of reducing the multiplicity of each point in the same code position by one at a time until zero, and the multiplicity of each point can be different. As an example, the proposed scheme is applied to a Chase-type decoding that has multiplicity two in the flipping points, and efficient hardware architectures are developed. For a (255, 239) RS code with eight test vectors, employing the proposed backward interpolation leads to 18% area reduction and 23% speedup compared to repeating the interpolation over the flipping points for each test vector.

Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can achieve substantial coding gain with polynomial complexity. Particularly, the low-complexity Chase (LCC) ASD decoding has better performance-complexity tradeoff. In the LCC decoding, 2ηtest vectors need to be interpolated over, and a polynomial selection scheme needs to be employed to select one interpolation output to send to the rest decoding steps. The interpolation and polynomial selection can account for a significant part of the LCC decoder area, especially in the case of long RS codes and large η . In this paper, simplifications are first proposed for a low-complexity polynomial selection scheme. Then a novel interpolation scheme is developed by making use of the simplified polynomial selection. Instead of interpolating over each vector, our scheme first generates information necessary for the polynomial selection. Then only the selected vectors are interpolated over. The proposed interpolation and polynomial selection schemes can lead to 162% higher efficiency in terms of throughput-over-area ratio for an example LCC decoder with η = 8 for a (458, 410) RS code overGF(210).