A method for parametric yield optimization which significantly reduces the simulation cost is proposed. The method assumes that the circuit performances ultimately determining yield can be approximated by computationally inexpensive functions of the inputs to the circuit simulator. These inputs are the designable parameters, the uncontrollable statistical variations, and the operating conditions of interest. The authors fit the approximating functions to data from a statistical experiment incurring relatively few runs of the simulator. For a given set of designable parameters, the fitted models predict the circuit performances as the uncontrollable parameters and operating conditions vary. The predictions lead to estimates of the parametric yield, which is then numerically maximized with respect to the designable parameters. The authors give a CMOS circuit example where sufficiently accurate predictions and good actual yield result from about 100 runs of the circuit simulator.>

iEDISON optimizes the transistor sizes of a circuit so that its performance is least sensitive to manufacturing process fluctuations. iEDISON considers three methods for design optimization, namely, the response surface method, the Taguchi method, and the nonnested experimental design method. These methods use experimental designs and regression models to explore the statistical performance variations. The efficiency of the system is demonstrated by an example on clock-skew minimization.>

A major cost in statistical analysis occurs in repeated system simulation as system parameters are varied. To reduce this cost, the system performances are approximated by regression models in terms of critical system parameters. These models are then used to predict the performance variations and parametric yield. This paper presents a systematic and computationally efficient method for deriving regression models of MOS VLSI circuit performances that can be used to estimate the parametric yield. This method consists of four fundamental steps: simulation point selection, model fitting and validation, model improvement, and parametric yield estimation. An average mean-squared error criterion is used to select an optimal set of points in the design space for circuit simulations, and the adequacy of the fitted regression model is checked rigorously. It will be shown through examples that accurate statistical performance models and parametric yield estimate for MOS VLSI can be derived by using four or five critical device parameters and a small number of circuit simulations.