This paper presents a new high speed dynamic programmable logic array (DPLA). The conventional level-restored mechanism is eliminated by using a straightforward CMOS inverter at the charge sharing node on the discharge path. This inverter acts as a voltage monitor and can reduce the voltage swing to 1/2 V/sub dd/ at the product lines or output lines. Thus power saving as well as high speed operation can be achieved. In addition, the smallest size inverter can be easily integrated to the design automation of DPLA without augmenting the structure of PLA. Furthermore, this design simplifies the design effort of buffering NAND gates and almost removes the serious glitch problem. Experimental results show that our proposed DPLA can be operated at high speed (>1GHz) with very small power delay product (PDP).

In this paper an efficient placement and global routing algorithm for the hierarchical FPGAs (HFPGAs) is developed. This algorithm is based on a modified k-way min-cut technique which recursively partitions a cluster in k sub-clusters to facilitate the architecture of the HFPGAs. Through this algorithm, both the placement and global routing can be done simultaneously. The results of on a set of MCNC benchmark circuits show that the proposed algorithm is very efficient.

In this paper we present an accurate and efficient modeling technique for CMOS circuits to facilitate the implementation of test generation (TG) and fault simulation (FS). The model is more general than any previous model. The accuracy is achieved because the device parameters, circuit configuration, and test patterns are considered. The efficiency is achieved due to the simplicity of the solution methods that require no complex circuit level simulation and any empirical constant. By using this model the "Byzantine General" problem during the FS and TG can be overcome. Experimental data show that SPICE like accuracy can be achieved without carrying out circuit-level simulation.

This paper presents BIFEST, an ATPG system that employs the built-in intermediate voltage test technique in an efficient ATPG process to deal with CMOS bridging faults. Fast and accurate calculations of the intermediate bridging voltages and the variant threshold tolerance margins on a resistive bridging fault model are presented. A PODEM-like, PPSFP-based ATPG process is developed to generate test patterns for faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits, called built-in intermediate voltage sensors (BIVSs). By this methodology, almost the same fault coverage as that employingIDDQtesting can be achieved with only logic monitoring required.

An accurate threshold voltage determination method for CMOS gates is presented that can be used to enhance the performance of test pattern generation (TPG) and fault simulation (FS). By using this model the "Byzantine General" problem during the FS and TPG can be overcome. Experimental data show that SPICE like accuracy can be achieved without carrying out circuit-level simulation.

In this paper, we present a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). The signal lines and devices of a PLA are represented as the edges and vertices of a directed graph, respectively. Through this graph model, most realistic PLA faults, including cross-point, stuck-at, break, and bridging faults, can be modeled and classified, and the maximal diagnosis resolution of a PLA can be determined. Moreover, the model can be easily transformed into a gate-level model. Hence, the work of automatic test-pattern generation for a PLA and for other random logic ran be done simultaneously. We also show that this representation can be extended to some logic design techniques such as logic minimization, folding, and decomposition for PLAs. Thus, this graph model can unify the data structure and operations required in PLA design and test.

In this paper we present two accurate and efficient modeling techniques for CMOS circuits to enhance the performance of test generation and fault simulation for bridging faults. The first one is a fault modeling technique for inter-gate bridging faults. The second one is an accurate threshold determination method. The accuracy of our model is achieved because all the following factors, including device parameters, voltage operation range of each logic value, resistance of ON-transistors, resistance of bridging faults, and test patterns are considered. The efficiency is achieved due to the simplicity of the solution methods that require no complex circuit level simulation. Experimental data show that SPICE like accuracy can be efficiently achieved.

This paper presents the BIFEST, an ATPG system that combines the conventional ATPG process and the built-in intermediate voltage test technique to deal with CMOS bridging faults. A PODEM-like, PPSFP-based ATPG process that can effectively and efficiently model the bridging fault effects is developed to process those faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits called built-in intermediate voltage sensors. By this methodology almost the same fault coverage as that employing IDDQ testing can be achieved with only logic monitoring required.

In-this paper, we present an efficient and accurate I/sub DDQ/ fault modeling technique for digital CMOS circuit. Both the normal and faulty "current" behaviors of a CMOS digital circuit can be described by this model. Also the parasitic capacitive and inductive parameters can be emulated. A formal method for creating this model from any given CMOS circuit is obtained. Using this model, circuit design of built-in current sensors (BICSs) can be designed and validated without introducing the actual circuit under test (CUT) which implanted a fault. Experimental data for the application to the design of BICSs is also given.

In this paper, a practical design for built-in current sensors (BICS's) is proposed. This scheme can execute current testing during the normal circuit operation with very small impact on the performance of the circuit under test (CUT). In addition, scalable resolutions and no external voltage/current reference make this design more effective and efficient than previous designs. Moreover this scheme can be used to monitor the current-related faults of both CMOS and non-CMOS circuits. Thus it is highly suitable for design for testability (DFT) on a multiple-chip module (MCM) or to be the current monitor on the test fixture under the quality test action group (QTAG) standard.>