As chip manufacturing approaches physical limits, the probability of defects due to specific chip layout structures has significantly increased. These defect-prone structures are known as lithographic hotspots. Pattern matching method is widely used in hotspot detection algorithms due to its efficiency and accuracy. However, traditional pattern matching algorithms face major challenges in both solution efficiency and flexibility for fuzzy matching. To overcome these limitations, an integer range-based deterministic finite automaton (r-DFA)-based layout pattern matching method supporting parallelization and fuzzy matching is proposed. Manhattan polygons in the layout are represented as multiple path strings, thereby transforming the pattern matching problem into a string regular expression search problem. To simplifies the construction of large integer range elements in fuzzy matching, the r-DFA is employed, enhancing construction efficiency and enabling the algorithm to achieve linear time complexity. Moreover, this approach focuses most of the matching process within each individual layout polygon, enabling parallelized matching across diverse layout polygons. Compared to the state-of-the-art, our approach supports fuzzy matching, and shows an average efficiency improvement of 1.23 times.

Electromagnetic interference (EMI) is an inevitable issue in power electronics applications. Although many kinds of solutions have been presented to attenuate EMI noise, there is still little research about the EMI suppression scheme utilized in multimode primary-side regulation (PSR) flyback converters. Targeting EMI regulation in multimode PSR flyback converter, a combo EMI suppression scheme comprised of frequency modulation and dual-slope gate driver is adopted to meet stringent EMI requirements, simplifying peripheral components and design of EMI filter. The proposed scheme is implemented in$0.18~\mu $m 5/40 V BCD process and occupies a die size (with pads) of$1.05\times 0.8$mm2. The experimental results show that the conducted EMI waveforms with line/neutral polarity can easily comply with regulations. The deviations of the output voltage are within ±1.3% under different inputs and loads while the peak effciency of 90% is achieved.

The power over Ethernet (PoE) technology has gained intensive attention in networking market owing to the advantages of compactness, flexibility, and cost in application. The automatic maintain power signature (MPS) function specified by IEEE standard extracts the periodic pulsed current to enable applications requiring low power modes. However, a large driving capacity is required due to a large MPS current above 10 mA, sacrificing a certain area. This brief proposes an adaptive MPS scheme, which reuses existing class regulator and delay timer to source a pulsed MPS current to meet the MPS requirements, saving an area of 0.0104 mm2. The proposed MPS scheme has been fabricated in 0.18-$\mu $m 120-V BCD process and the area is$1.37\times 1.00$mm2. The experimental results show that the proposed PoE interface draws a pulsed current with a period of 312 ms and 25.6% duty cycle to address the issue of MPS absence in very low-power standby modes.

Unlike traditional offline courses, where the enrollment number is generally fixed, massive open online courses (MOOCs) often exhibit significant disparities in the enrollment number across different sections. Namely, this number can vary by several or even hundreds of times depending on the MOOC sections. To this end, this study proposes a remote FPGA-based experimental teaching system with two main innovations. First, a software-hardware co-work framework is designed to divide a single physical FPGA into multiple independently virtual FPGAs, allowing for multiple users to use the same physical FPGA concurrently. Second, an "X86 CPU+Multi-PYNQ" collaborative computing system supporting up to 16 PYNQs for parallel computing is designed. This system uses an X86 CPU as a main processor to distribute computing tasks to the PYNQ-cluster for scheduling FPGA parallel computations, which enables a single user to use multiple FPGAs concurrently. Therefore, the proposed system can effectively address the problem of underutilized boards in MOOCs where the enrollment number is smaller than the number of available FPGA boards. In summary, the system proposed in this paper can effectively mitigate the conflict between the number of students and the number of FPGA boards in MOOCs.

This article presents a constant voltage control scheme to improve the transfer efficiency and output voltage accuracy for single-stage AC-DC converters. The proposed scheme also has the advantage of low cost because of the simple application and few peripheral devices. To realize above features, the peak current and frequency curves with high efficiency are selected by analyzing the power losses of the applied topology. A voltage self-compensation circuit is designed to improve the output accuracy, especially the output voltage below 5V. Furthermore, a multi-stage startup circuit is also proposed to reduce the output voltage overshoot. To verify the feasibility of the proposed constant voltage control scheme, a BUCK controller adopting the proposed control scheme has been designed and fabricated with$0.18~\mu \text{m}$BCD process. Using the proposed controller, the peak efficiency of the prototype can reach as high as 66.9%, 78.9% and 82.8% under 115Vac input and 3.3V@300mA, 5V@300mA and 12V@300mA respectively. The load regulation is counted to be within ±1%.

Current image compression algorithms based on transforms can achieve ideal performance for natural images, but do not do well with synthetic aperture radar (SAR) images. We propose a learned compression framework with pyramidal features and quality enhancement to fully exploit the redundancy among image pixels and to improve the compression bitrate and reconstruction quality. Based on the variational autoencoder (VAE) architecture, pyramidal decomposition is performed at the first autoencoder to extract both global and coarse feature maps. The latent distribution is modeled by the second hyperprior autoencoder with a single-Gaussian model for more accurate and flexible entropy estimation. Universal quantization is applied to consolidate the entropy estimation accuracy of the hyperprior network. To further improve reconstruction quality, a residual dense network (RDN) is adopted to fully capture local and global features. Experimental results demonstrate that the proposed framework provides a better rate-distortion tradeoff than standard codecs such as JPEG, JPEG2000, and learning-based methods on both the Sandia and ICEYE datasets.

Given the uniqueness of synthetic aperture radar (SAR) images, traditional optical image compression algorithms cannot fully exploit their redundant information. To improve SAR image compression in terms of rate–distortion performance and visual perception, an end-to-end SAR image compression convolutional neural network (CNN) model based on a variational autoencoder is proposed. The proposed CNN model consists of a main autoencoder and a hyper autoencoder. To reduce dependencies in latent space, a joint transform of linear CNN and nonlinear generalized divisive normalization (GDN) activation is applied in the main autoencoder. Moreover, residual blocks are combined with the transforms to boost the efficiency of feature learning and make use of subpixels to improve the quality of reconstructed images. Instead of a fixed entropy model, a conditioned entropy model that works with a hyperprior network is used to learn the distribution of latents, which helps to further improve the compression quality. During training, the model is optimized by evaluating the rate–distortion performance. The experimental results show that the proposed method can achieve better distortion performance than JPEG, JPEG2000, and the available CNN-based method in terms of objective evaluation criteria and human vision perception quality.

With the increasing complexity of modern design, mixed-cell-height designs have become more popular, which makes the legalization problem more challenging. In this article, a robust negotiation-based legalizer (NBLG) is proposed to reduce average displacement and maximum displacement for mixed-cell-height circuits with considering the fence region and technology constraints. By dissecting the main components of the negotiation-based method, we divide the placement grid in terms of placement sites and reformulate the legalization problem as a resource allocation task. We then allow all movable cells to gradually remove overlaps in a surrounding window with two individual techniques: 1) isolation point and 2) adaptive penalty function. We also adopt a deterministic multithreading technique to accelerate the convergence of our algorithm. Experimental results show that our legalizer achieved the minimal average displacement and maximum displacement in a reasonable runtime compared with state-of-the-art methods.