Laser Heterodyne Radiometry is a powerful technique that is becoming popular in atmospheric spectroscopy because of its ability to amplify signals and achieve high spectral resolution. Current designs employ a narrow-band analog radio design focused on time domain analysis combined with laser scanning to measure a spectrum. This study evaluates an alternative approach using a wideband radio design combined with digital processing focused on the frequency domain to generate a spectrum without laser scanning. A recorded signal is converted into the frequency domain using Fast Fourier Transform (FFT) and impacts of FFT length and number of time averages on the generated absorption spectrum are compared. Counterintuitively, longer FFT lengths decrease the signal fit while more averaging conveys better performance.

This paper introduces a methodology for hardware-software co-implementation, designed to simplify the System-on-Chip (SoC) design process when attempting to time-multiplex hardware. The approach streamlines the transformation of complex algorithms into efficient SoC implementations by providing a recipe for seamless hardware-software partitioning. As a case study, the methodology is applied to the Extrapolated Single Propagation Particle Filter algorithm for geo-locating sources of radio frequency interference and results demonstrate a considerable speed-up when using a time-multiplexed implementation.

High-Level Synthesis (HLS) is a common approach for programming Field Programmable Gate Arrays (FPGAs) across various applications. HLS tools enable novice hardware designers to synthesize Register Transfer Level (RTL) representations from high-level software programming languages. However, adhering to a specific coding style and understanding the performance disparities post-synthesis can challenge new HLS users. This work introduces an Instruction Block Diagram (IBD) framework using inputs from the Vitis HLS Schedule Viewer to enhance the understanding of HLS compiler interpretation for the user code and guide optimization to improve efficiency.

With the widespread deployment of wireless sensor networks and the nascent Internet of Things (IoT), enabling devices to be connected in wider, and denser ecosystems, improved wireless security has become of paramount importance. Limited power and computational resources of these devices, however, render sophisticated algorithms and protocols not suitable for all the devices. Radio Frequency (RF) fingerprinting has the potential to enhance the security and with increasing popularity of deep learning, RF fingerprinting approaches have attracted attention with new techniques proposed. In this paper we present a novel waveform domain-based approach operating on images generated from captured raw samples for device identification. The use of images, as opposed to raw sample sequences, enables the capture of information from theoretically infinite number of raw samples without impacting the structure and the complexity of the subsequent deep learning processing. We use a simple Dense Neural Network (DNN) model which is implemented and trained on waveform images generated from the captured raw samples. The efficacy of the proposed approach is demonstrated using over-the-air signals captured from 12 Zigbee devices, with the proposed approach achieving near 99% identification accuracy.

This paper proposes a time-frequency (TF) domain technique for detecting the presence of automatic dependent surveillance-broadcast (ADS-B) interference signals in radio astronomy applications. The proposed technique uses a priori knowledge about the ADS-B signal's frequency information and compares it with the received signal's spectrogram time slices via the cosine similarity function. In the presence of ADS-B signals, the similarity levels are higher, whereas in their absence the levels are lower. Hence, the proposed approach exploits this to detect the presence of such signals. Simulation results using signals from the Parkes radio telescope show the efficacy of the proposed method in detecting the presence of ADS-B signals when compared with other classic detectors.

This work presents an automated flow for producing fault-tolerant Field Programmable Gate Array (FPGA) systems. The flow uses the TLegUp High Level Synthesis (HLS) tool to generate triplicated register-transfer level designs for algorithms expressed in the C language and Vivado design suite for their implementation on Xilinx 7-series FPGAs. TLegUp has been extended to partition the design into a number of Triple Modular Redundant (TMR) components, which can be optionally floorplanned during their implementation. Partitioning the TMR design into a network of smaller TMR components and isolating their modules through flooplanning increases system reliability. We implemented a fine- and a coarse grain approach to partition the design, whereby the former approach uses a network flow algorithm to partition the application's Data Flow Graph (DFG) at the instruction level, while the latter uses the same algorithm to partition the design at the C function level. Results reveal that both approaches provide similar reliability enhancement to the system, but function-level partitioned designs are smaller and faster.

Coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their performance and flexibility advantages. Typically, CGRAs incorporate many processing elements in the form of an array, which is suitable for implementing spatial redundancy, as used in the design of fault-tolerant systems. This article introduces a recovery time model for transient faults in CGRAs. The proposed fault-tolerant CGRAs are based on triple modular redundancy and coding techniques for error detection and correction. To evaluate the model, several kernels from space computing are mapped onto the suggested architecture. We demonstrate the tradeoff between recovery time, performance, and area. In addition, the average execution time of an application including recovery time is evaluated using area-based error-rate estimates in harsh radiation environments. The results show that task partitioning is important for bounding the recovery time of applications that have long execution times. It is also shown that error-correcting code (ECC) is of limited practical value for tasks with long execution times in high radiation environments, or when the degree of task partitioning is high.

Space processing applications deployed on SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to radiation-induced Single Event Upsets (SEUs). Compared with the well-known SEU mitigation solution—Triple Modular Redundancy (TMR) with configuration memory scrubbing—TMR with module-based error recovery (MER) is notably more energy efficient and responsive in repairing soft-errors in the system. Unfortunately, TMR-MER systems also need to resort to scrubbing when errors occur between sub-components, such as in interconnection nets, which are not recovered by MER. This article addresses this problem by proposing a fine-grained module-based error recovery technique, which can localize and correct errors that classic MER fails to do without additional system hardware. We evaluate our proposal via fault-injection campaigns on three types of circuits implemented in Xilinx 7-Series devices. With respect to scrubbing, we observed reductions in the mean time to repair configuration memory errors of between 48.5% and 89.4%, while reductions in energy used recovering from configuration memory errors were estimated at between 77.4% and 96.1%. These improvements result in higher reliability for systems employing TMR with fine-grained reconfiguration than equivalent systems relying on scrubbing for configuration error recovery.

We present TLegUp, an extension of LegUp, that automatically generates Triple Modular Redundant designs for FPGAs from C programs. TLegUp is expected to improve the productivity of application designers for space, to allow designers to experiment with alternative application partitioning, voter insertion and fault-tolerant aware scheduling and binding algorithms, and to support the automatic insertion of the infrastructure needed to run a fault-tolerant system. In this paper, we examine TLegUp's capacity to make use of both combinational and sequential voters by triplicating a design before scheduling and binding occur. In contrast, traditional RTL-based tools are constrained to use only combinational voters so as to preserve the scheduling and binding of the design, critical path lengths are consequently increased. We compare the use of sequential and combinational voters for a range of benchmarks implemented on a Xilinx Virtex-6 FPGA in terms of: (i) maximum operating frequency, (ii) latency, (iii) execution time, and (iv) soft-error sensitivity. Compared to the use of combinational voters, the use of sequential voters reduces the application execution time on the CHStone benchmark suite by 4% on average.

Field-Programmable Gate Arrays (FPGAs) are susceptible to radiation-induced Single Event Upsets (SEUs). A common technique for dealing with SEUs is Triple Modular Redundancy (TMR) combined with Module-based configuration memory Error Recovery (MER). By triplicating components and voting on their outputs, TMR helps localize the configuration memory errors, and by reconfiguring the faulty component, MER swiftly corrects the errors. However, the order in which the voters of TMR components are checked has an inevitable impact on the overall system reliability. In this paper, we outline an approach for computing the reliability of TMR-MER systems that consist of finitely many components. Using the derived reliability models we demonstrate that the system reliability is improved when the critical components are checked more frequently for the presence of configuration memory errors than when they are checked in round-robin order. We propose a genetic algorithm for finding a voter checking schedule that maximizes system reliability for systems consisting of finitely many TMR components. Simulation results indicate that the mean time to failure of TMR-MER systems can be increased by up to 100% when Variable-Rate Voter Checking (VRVC) rather than round robin, is used. We show that the power used to eliminate configuration memory errors in an exemplar TMR-MER system employing VRVC is reduced while system reliability remains high. We also demonstrate that errors can be detected 30% faster on average when the system employs VRVC instead of round robin for voter checking.

FPGAs are promising candidates for computational tasks in space. However, they are susceptible to radiation-induced errors in their configuration memory. The recovery of configuration errors, either by device scrubbing or by module-based recovery, involves a series of reads and writes to the FPGA's configuration port, and is efficiently performed on-chip by a fast, flexible and reliable reconfiguration controller. In this work, we consider the reliability improvement of the recently proposed Programmable Configuration Controller (PCC), a soft reconfiguration controller that has been shown to be both fast and flexible, but whose reliability, particularly in the face of radiation-induced configuration errors, has not until now been studied. To ensure that the PCC itself is reliable, we propose the use of traditional Triple Modular Redundant (TMR) combined with a novel software-based interrupt-driven fault recovery process that leverages hardware-accelerated configuration access. We report on our design space exploration to balance the utilization, error recovery performance, and reliability of the PCC. In extremely harsh radiation environments, the Mean Time to Failure of the PCC is as high as 25 years, compared with 3.5 hours for its non-protected counterpart, and that it takes as little as 27 ms to recover from a configuration memory error affecting the PCC.

Field-Programmable Gate Arrays (FPGAs) provide ideal platforms for meeting the computational requirements of future space-based processing systems. However, FPGAs are susceptible to radiation-induced Single Event Upsets (SEUs). Techniques for dynamically reconfiguring corrupted modules of Triple Modular Redundant (TMR) components are well known. However, most of these techniques utilize resources that are themselves susceptible to SEUs to transfer reconfiguration requests from the TMR voters to a central reconfiguration controller. This paper evaluates the impact of these Reconfiguration Control Networks (RCNs) on the system's reliability and performance. We provide an overview of RCNs reported in the literature and compare them in terms of dependability, scalability and performance. We implemented our designs on a Xilinx Artix-7 FPGA to assess the resulting resource utilization and performance as well as to evaluate their soft error vulnerability using analytical techniques. We show that of the RCN topologies studied, an ICAP-based approach is the most reliable despite having the highest network latency. We also conclude that a module-based recovery approach is less reliable than scrubbing unless the RCN is triplicated and repaired when it suffers configuration memory errors.

High-reliability SRAM-based Field Programmable Gate Array (FPGA) designs that are deployed in space are commonly triplicated to mask Single Event Upsets (SEUs) and employ either scrubbing or modular reconfiguration to recover from radiation-induced configuration memory errors. Scrubbing benefits from vendor support and clears errors anywhere in the design but suffers from longer recovery times and higher energy use. Module-based error recovery is more energy efficient and responsive but repairs only corrupted TMR modules, leaving the supporting parts of the design such as pins or routing that are not included in the modules unrecovered. This paper proposes and assesses a hybrid technique we refer to as Frame- and Module-based Error Recovery (FMER) that uses modular reconfiguration to repair faulty TMR modules and otherwise scrubs the supporting parts of the design. We derive and compare the reliability, availability and power consumption of TMR-based System on Chip (SoC) designs that incorporate FMER, modular reconfiguration alone, blind scrubbing and no recovery. Our results reveal that FMER has the highest reliability and availability of the studied techniques in high radiation environments or when a mission's energy budget is limited.

FPGAs are promising candidates for computational tasks in space applications. However, they are susceptible to radiation-induced errors, the most common failure being due to the corruption of their configuration memory. Module-based partial reconfiguration and frame-based scrubbing are the two most commonly used techniques for detecting and recovering from configuration memory errors. Both methods require user-designed reconfiguration controllers (RC) to read and write FPGA configuration memory data. This paper proposes a Programmable Configuration Controller (PCC) specifically designed for fault-tolerant applications. PCC has a soft Application Specific Instruction Set Processor (ASIP) architecture. The PCC is software programmable using the C language, which allows it to be used in a wide variety of fault-tolerant applications with minimal design and/or hardware overhead. PCC also has instruction extensions to accelerate commonly-used reconfiguration operations such as reading and writing configuration data. Through 5 case studies, we demonstrate that the use of an ASIP architecture for reconfiguration control in applications prone to radiation-induced corruption strikes the right balance between speed, resource utilization and flexibility.

SRAM-based Field-Programmable Gate Arrays (FPGAs) are susceptible to radiation-induced Single Event Upsets (SEUs). Techniques for partially reconfiguring corrupted modules of Triple Modular Redundant (TMR) FPGA-based designs have been described in the literature. Most of these techniques require some form of network-on-chip for aggregating voter error messages from the system's TMR components to a central reconfiguration controller in order to trigger the partial reconfiguration of modules when they become faulty. The frequency at which TMR components fail in the system depends on their soft-error vulnerability. However, most error recovery techniques adopt a static voter error checking schedule, which leads to delays in checking TMR components with high failure probability. In this paper we propose a Voter Scheduling Engine (VSE) for dynamically prioritizing and managing TMR voter checks so as to minimize the error detection time in the system and to thereby maximize the system's reliability. Software and hardware implementations of the VSE are proposed. Moreover, we have implemented the classic static voter checking schedule and the VSE on a real TMR system and evaluated the reliabilities of both approaches for varying radiation environments. Results demonstrate that the likelihood of system failure can be decreased by up to 50% when the VSE, rather than static voter checking, is incorporated into the TMR system.

Space processing applications deployed on SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to radiation-induced Single Event Upsets (SEUs). Compared with the well-known SEU mitigation solution - Triple Modular Redundancy (TMR) with configuration memory scrubbing - TMR with module-based error recovery (MER) is notably more energy efficient and responsive in repairing soft-errors in the system. Unfortunately, TMR-MER systems also need to resort to scrubbing when errors occur in sub-components, such as nets, which are not recovered by MER. This paper addresses this problem by proposing a fine-grained module-based error recovery technique that without additional system hardware can localize and correct errors that classic MER fails to do. We evaluate our proposal via a fault-injection campaign on a Xilinx Artix-7 application circuit and compare the reliability, the error correction latency and the energy cost of repairing errors, of our proposal with those of a conventional MER approach and with periodic and on-demand blind scrubbing. We find the reliability of our proposal to be the highest and the energy expenditure to be the lowest amongst those methods considered.

Global navigation satellite systems (GNSS) and, in particular, the global positioning system (GPS) have become ubiquitous in safety critical infrastructure. Vulnerability of GNSS to radio frequency interference (RFI) from either intentional (jamming) or unintentional sources is an ever growing concern. Hence, GNSS itself has become critical infrastructure which must be protected and its vulnerability to interference alleviated. As the RFI source is unknown a priori, passive localization systems are required; this adds an order of difficulty when compared with transmitter location systems with known and cooperative sources. The need for rapidly localizing the RFI leads to sensor network techniques which consist of spatially distributed sensor nodes (SNs). The localization systems typically use the received signal strength (RSS), source angle of arrival (AOA)/ direction of arrival (DOA), time difference of arrival (TDOA) or a combination of AOA(DOA)/TDOA or frequency difference of arrival (FDOA) measurements to estimate the RFI position. This paper provides an overview of existing systems from the literature and a comparison of these different interference geo-localization techniques.

Field-Programmable Gate Arrays (FPGAs) provide an ideal platform for meeting the performance, cost and flexibility requirements of on-board processing in spacebourne applications. However, given the reliance on SRAM-based configuration memory, off-the-shelf FPGAs are vulnerable to radiation-induced Single Event Upsets (SEUs). The detection and mitigation of the effects of SEUs is therefore of paramount importance. Moreover, in time critical applications, it is also desirable to detect and recover from errors rapidly. Techniques for partially reconfiguring a corrupted module of a Triple Modular Redundant (TMR) implementation have been described in the literature. In this paper we address the speed penalty incurred with such techniques and provide a generalized approach for alleviating it. The results indicate that the speed penalty can be greatly reduced enabling rapid recovery from SEUs in reconfigurable hardware.

Field-Programmable Gate Array (FPGA) systems provide an ideal platform for meeting the computation requirements for future on-board processing. FPGAs, however, are susceptible to radiation-induced Single Event Upsets (SEUs). Techniques for partially reconfiguring a corrupted module of a Triple Modular Redundant (TMR) implementation have been described in the literature. In this paper we detail the design of a reconfiguration network that provides the infrastructure to enable SEU recovery in FPGAs. The reconfiguration network's structure and operation is detailed along with performance analysis using results from simulated and implemented designs. The results indicate that total error recovery time from SEUs is dominated by the reconfiguration delay, and that the communication delay of the reconfiguration network is relatively small.

Field-Programmable Gate Array (FPGA) systems are increasingly susceptible to radiation-induced Single Event Upsets (SEUs). Application circuits are most commonly protected from SEUs using Triple Modular Redundancy (TMR) and scrubbing to eliminate configuration memory errors. This paper focuses on implementing circuits that recover from SEUs within a specified maximum recovery period, a practical requirement not previously addressed. We develop a recovery time model, describe a scalable reconfiguration control network, and investigate the performance of a representative TMR system implemented using our approach. The results demonstrate that modular reconfiguration eliminate configuration errors more responsively and using less energy than scrubbing. However, these benefits are achieved at the cost of additional area, minor speed penalties, and greater design complexity.

This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the image-rejection-ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

This paper deals with and details the design and implementation of a low-power; hardware-efficient adaptive self-calibrating image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Hybrid strength-reduced and re-scheduled data-flow, low-power implementation of the adaptive self-calibration algorithm is developed and its efficiency is demonstrated through simulation case studies. A behavioral and structural model is developed in Matlab as well as a low-level architectural design in VHDL providing valuable test benches for the performance measures undertaken on the detailed algorithms and structures.

This paper provides an overview of the sources and effects of the RF impairments limiting and rendering the performance of the future wireless communication transceivers costly as well as hindering their wide-spread use in commercial products. As transmission bandwidths and carrier frequencies increase effect of these impairments worsen. This paper studies and presents analytical evaluations of the performance degradation due to the RF impairments in terms of bit-error-rate and image rejection ratio. The paper also give highlights of the various aspects of the research carried out in mitigating the effects of these impairments primarily in the digital signal processing domain at the baseband as well as providing low-complexity hardware implementations of such algorithms incorporating a number of power and area saving techniques

Global navigation satellite system (GNSS) receivers require solutions that are compact, cheap and low-power, in order to enable their widespread proliferation into consumer products. Furthermore, interoperability of GNSS with non-navigation systems, especially communication systems will gain importance in providing the value added services in a variety of sectors, providing seamless quality of service for users. An important step into the market for Galileo is the timely availability of these hybrid multi-mode terminals for consumer applications. However, receiver architectures that are amenable to high-levels of integration will inevitably suffer from RF impairments hindering their easy widespread use in commercial products. This paper studies and presents analytical evaluations of the performance degradation due to the RF impairments and develops algorithms that can compensate for them in the DSP domain at the base band with complexity-reduced hardware overheads, hence, paving the way for low-power, highly integrated multi-mode GNSS receivers

In this paper, we propose a low-complexity architecture for the implementation of adaptive IQ-imbalance compensation in quadrature zero-IF receivers. Our blind IQ-compensation scheme jointly compensates for IQ phase and gain errors without the need for test/pilot tones. The proposed architecture employs early-termination of the iteration process; this enables the powering-down of the parts of the adaptive algorithm thereby saving power. The complexity, in terms of power-down efficiency is evaluated and shows a reduction by 37-50 % for 32-PSK and 37-58 % for 64-QAM modulated signals

An adaptive self-calibrating image rejection receiver is described, containing a modified weaver image rejection mixer and a digital image rejection processor (DIRP). The blind source-separation-based DIRP eliminates the I/Q errors improving the image rejection ratio (IRR) without the need for trimming or use of power-hungry discrete components. Hardware complexity is minimal, requiring only two complex-coefficients; hence it can be easily integrated into the signal processing path of any receiver. Simulation results show that the proposed approach achieves 75-97 dB of IRR.

Phase and gain mismatches between the I and Q analog signal processing paths of a quadrature receiver are responsible for the generation of image signals which limit the dynamic range of a practical receiver. We analyse the effects of these mismatches and propose a low-complexity blind adaptive algorithm to minimize this problem. The proposed solution is based on two, 2-tap adaptive filters, arranged in an adaptive noise canceller (ANC) set-up. The algorithm lends itself to efficient real-time implementation with minimal increase in modulator complexity.