In this paper, we explore a low area-time elliptic curve point multiplication (ECPM) hardware accelerator over Curve25519. Firstly, we analyze the correlation of the data hazards of LADDER (main operation), the number of pipeline stages in modular multiplication (MM), and the number of iterations of multiplier in MM, and then establish an equation among them. Based on this equation, a new iterative hardware model of modular multiply-accumulator (MMAC) with stage=10 using a 128-bit multiplier, and a new LADDER scheduling are proposed to support high-performance scenarios for Curve25519 ECPM. Secondly, based on the proposed method, we propose a new 255-bit iterative MMAC. Finally, we explore the trade-off between area and time, present an efficient hardware design to accelerate the Curve25519 ECPM. The proposed accelerator is implemented on the Xilinx XC7Z020 platform. The results show that the proposed accelerator costs 2,367 Slices and 36 DSP blocks, with a clock frequency of 298 MHz. When calculating one Curve25519 ECPM, compared to previous designs with the best area*time (AT) value, the AT value of this design is 220% superior to their design, while the area and time have improved by 52% and 108% compared to theirs, respectively.

Physical Unclonable Functions (PUFs) are vital for secure hardware authentication due to their intrinsic uniqueness. RRAM-based PUFs offer advantages such as compactness, low power, and CMOS compatibility, but suffer from reliability issues under environmental stress such as temperature and aging. This work proposes a self-checking RRAM-based PUF architecture using a resistance-delay mapping method to generate reliability-quantified challenge-response pairs (CRPs). A configurable Delay Amplification Chain (DAC) converts device-to-device(D2D) resistance variations into measurable timing differences, ensuring stable operation from -55°C to 125°C and ± 10% VDD fluctuations. A built-in self-checking mechanism filters unstable CRPs via complementary delay biases during the dark bit filtration stage, reducing bit error rate (BER) from 5.2% to 0.77%. A hierarchical framework further classifies CRPs into 11 reliability levels, enabling adaptive key management. Implemented in 180nm CMOS/RRAM technology, the design achieves 49.61% inter-chip and 49.80% reconfig Hamming distances across 50 instances, showing strong uniqueness and reconfigurability. No BER degradation was found in 10-year aging simulations. The design meets NIST SP800-22 randomness standards and offers a scalable and entropy-aware solution for IoT security.

This paper explores more efficient LUT6-Based multiplier for Montgomery Modular Multiplication (MMM) on FPGA. Firstly, we analyze and compare the LUT6-Cost of multipliers using previous Radix-4/8/16 Booth methods. Based on the LUT6, we propose an improved LUT6-Based Radix-16 Booth method for Coarsely Integrated Operand Scanning (CIOS) MMM. When the value of multiples remains unchanged for a period of time, this method uses LUT6-Based SDP-RAM to store multiples instead of MUX to select, which effectively reduces the LUT6-Cost of Decode. Secondly, we propose a new LUT6-Based CIOS MMM using the proposed method. Finally, we explore the trade-off between area and latency, present an efficient LUT6-Based MMM hardware design (LUT6-MM) to accelerate CIOS MMM. The LUT6-MM is a scalable, parametric, and reconfigurable design, it is implemented on Xilinx Virtex-7 FPGA. When performing 1024/2048-bit MMM, the results show that the area*latency products (ALPs) of LUT6-MM (w1=32,w2=128) are 51.1%/48.8% of the previous state-of-art scalable and parametric LUT6-Based reference (Non-Reconfigurable, Not using DSP).

Montgomery Modular Multiplication (MMM) is widely used in many public key cryptography systems. This paper presents a Flexible Low Area-Latency MMM (FLALM) implementation, which supports Generic Montgomery Modular Multiplication (GMM) and Square Montgomery Modular Multiplication (SMM) operations. A new SMM schedule for the Finely Integrated Product Scanning (FIPS) GMM algorithm is proposed to accelerate SMM with tiny additional design. Furthermore, a new FIPS dual-schedule is proposed to solve the data hazards of this algorithm. Finally, we explore the trade-off between area and latency, and present the FLALM to accelerate GMM and SMM. The FLALM is implemented on FPGA (Virtex-7 platform). The results show that the area*latency (AL) value of FLALM (wordsize$w$=128) is 38.1% and 44.7% better than the previous state-of-art scalable references when performing 1024-bit and 2048-bit GMM, respectively. Moreover, when computing SMM, the advantage of AL value is raised to 73.7% and 86.3% respectively.

Abstract In this paper, a secure plaintext‐related image encryption scheme based on compressive sensing and a tent‐sine system is proposed. First, the discrete wavelet transform (DWT) is used to transform the plain image to get a coefficient matrix. Second, several chaotic sequences generated by the tent‐sine chaotic map are used to scramble the coefficient matrix and construct a measurement matrix. Afterward, compressive sensing is performed on the coefficient matrix to obtain a small‐sized encrypted image. Finally, an image encryption scheme related to plaintext is designed. In particular, the proposed system uses the original image information to participate in the encryption process, ensuring the high sensitivity of the cryptosystem to minor differences in the plain image and good performance on resisting known/selected plaintext attacks. Furthermore, to convey the plaintext‐related parameters to the receiver, the dimension of the ciphertext image is expanded, and the parameters are embedded into the ciphertext image. Simulation results and security analysis show that the proposed image encryption system has strong plaintext sensitivity and robustness for effectively resisting various typical attacks such as brute‐force attacks, statistical attacks, and differential attacks.

In this paper, general logic cell and module designs in basic digital signal processing (DSP), for transparent, flexible chips and wearable electronics are presented. Modified Circuits from ratioed logic and pass transistor logic styles are modified and proposed, based on n-type-only indium tin oxide (ITO) stabilized ZnO thin-film transistors (TFTs) process. Elaborations on logic circuits with purely n-type TFT transistors were carried out to extend the logic swing of circuit outputs and accelerate the signal propagation in complex logic functions with simplified pull-up/pull-down or passive networks. To implement logic complexes on multiple OR-of-ANDs functions with better performance, tailored active controlled ratioed logic style is adopted with faster speed and smaller area by simplifying the transistor networks properly. All the circuits were fabricated on transparent glass plate. The featured 2-input/3-input XOR gate, 4-1 MUX and D flip flop (DFF) can operate with maximum featured delays of 2-$6~\mu \text{s}$at 5 V power supply, with comparatively over 50% less delays and areas than other state-of-art works. The featured 4-bit adder performs maximum$16.41~\mu \text{s}$delay at 5 V in measurement. A 4-bit multiplier is also presented based on the adder and DFF. These proposed TFT circuits exhibited smaller area with relatively moderate-high performance in comparison, which were promising building blocks for transparent flexible DSP electronics with low-speed requirements.

In this paper, an improved motion planning scheme is proposed for surgical robot control with multiple active constraints, including joint constraints, joint velocity constraints and remote center of motion constraints. It introduces an improved recurrent neural network (RNN) to optimize the online motion planning respect to multiple constraints. The demonstrated surgical operation trajectory is derived using teaching by demonstration. An improved motion planning scheme using the novel recurrent neural network is then designed to achieve the accurate task tracking under the multiple constraints. The general quadratic performance index is adopted to represent the constraints. Finally, the effectiveness of the proposed algorithm is demonstrated using KUKA LWR4+ robot in a lab setup environment.