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Xin Fan 0009

dblp:87/3021-9 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2026
0009-0008-4658-8192ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Cryptographic primitives and cryptanalysis · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 77% Integrated circuit design · 23%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cryptographic primitives and cryptanalysis › homomorphic encryption
fully homomorphic encryption
0.912025
Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator · ACM Trans. Archit. Code Optim. 2025
Cryptographic primitives and cryptanalysis › homomorphic encryption › fully homomorphic encryption › TFHE
programmable bootstrapping
0.912025
Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator · ACM Trans. Archit. Code Optim. 2025
Cryptographic primitives and cryptanalysis › homomorphic encryption › fully homomorphic encryption
TFHE
0.912025
Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator · ACM Trans. Archit. Code Optim. 2025
Hardware accelerators and domain-specific architectures
cryptographic accelerator
0.912025
Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator · ACM Trans. Archit. Code Optim. 2025
Integrated circuit design
ASIC design
0.312025
Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator · ACM Trans. Archit. Code Optim. 2025

Methods — techniques the papers use, named apart from their topics

special-prime processing element · 1.7hybrid dataflow · 1.7
YearPublicationVenuePosition
2026 FlashGEMM: Mesh-Aware Efficient GEMM for 3D-Stacked LLM Accelerators
abstract
Large language models (LLMs) are foundational to artificial general intelligence (AGI), while imposing stringent hardware demands in computational power and memory bandwidth. To meet these demands, recent advances in hybrid bonding offer new opportunities through high-bandwidth, low-latency logic-memory 3D integration. Due to the spatial distribution of bandwidth in 3D-stacked DRAM, accesses to remote DRAM banks need to traverse the network-on-chip (NoC). Since GEMM is the dominant operator in LLM workloads, we analyze existing distributed GEMM algorithms and show that they suffer from communication inefficiency on mesh topologies. To address these challenges, we present FlashGEMM, a mesh-aware distributed GEMM algorithm that achieves efficient communication-computation overlap and optimized execution flow for 3D-stacked LLM accelerators. Evaluations show that FlashGEMM delivers up to 1.50× improvement in time-to-first-token (TTFT) and 7.11× improvement in throughput over prior methods.
Xin Fan 0009, Zhenhua Zhu 0002, Zhao Zhang 0001, Yuan Xie 0001
DATE1
2025 Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator
abstract
Fully homomorphic encryption over torus (TFHE) enables the execution of arbitrary functions on encrypted data through programmable bootstrapping (PBS). However, performing all operations on ciphertext during PBS results in high computational and memory requirements, limiting the deployment of PBS in real-world scenarios. Previous TFHE accelerator designs have attempted to improve performance by employing specific dataflow and functional units, but these techniques may require large off-chip bandwidth or on-chip storage when scaling up computation capacity. Additionally, the design of specialized functional units may limit the utilization of computation units when facing dynamic secure parameter settings. To address these challenges and further improve PBS throughput in TFHE, we propose Matrix , an ASIC-based architecture that balances off-chip bandwidth and on-chip storage according to the execution flow of PBS. In Matrix , we utilize a unified special-prime-based processing element (PE) that achieves high utilization with minimal resource overhead. Furthermore, we propose a hybrid PBS dataflow that can efficiently reduce computation complexity and memory requirements. Compared to state-of-the-art TFHE accelerators, Matrix achieves 1.43 × -5.66 × throughput improvement for PBS. For ZAMA Deep-NN benchmark, we achieve 525.60× and 68.06× speedup compared to CPU and GPU, respectively. 1
Ling Liang 0003, Fahong Zhang 0004, Zhirui Li, Xin Fan 0009, Dimin Niu, Meng Li 0004, Zhiyong Li 0016, Zongwei Wang 0001, Hongzhong Zheng, Yimao Cai, Yuan Xie 0001
ACM Trans. Archit. Code Optim.6