This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed gated-clock tree synthesizer for the first issue, and timing constraints generator and clock delay estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts.

A new technology re-mapping method named LDR (Layout Driven Re-synthesis), which is applied after placement, is proposed. LDR executes re-mapping and re-placement simultaneously in order to minimize power consumption with placement information. High switching activity nets are concealed inside the re-mapped cells or are shortened by re-placement in LDR. To estimate power consumption, LDR uses static power estimator for combinational circuits. LDR also calculates wire capacitances accurately based on placement information to evaluate power. Experimental results show that 20 % power reduction compared with original circuits is performed by proposed method. 1 Introduction Lowpower LSI design becomes important. For example, for portable equipments, power consumption is critical design concern because of limited battery life time. For high performance computers, expencive package cost for cooling is major problem. There are many conventional methods to reduce power consumption in logic s...

We propose an incremental probabilistic approach to calculate the signal probabilities and switching activities of the internal nodes of sequential logic circuits. Spatio-temporal correlations are fully considered by using Multi-Terminal Binary Decision Diagrams (MTBDD) with real number valued terminals. The running time of our approach is short because the depth of the MTBDD does not depend on circuit size but only on the user-specified unrolling number, which is usually 2 or 3. Experimental results show that our approach is 100-times faster than logic simulation and 10-times more accurate than the previous approach which ignores all correlations.

This paper proposes a fanout-tree restructuring algorithm for post-placement timing optimization to meet timing constraints. The proposed algorithm restructures a fanout-tree by finding a tree in a graph which represents a multi-terminal net, and inserts buffer cells and resizes cells based on an accurate interconnection RC delay without degrading routability. The algorithm has been implemented and applied to a number of layout data generated by timing driven placement. Application results show a 17% reduction in circuit delay on the average.

This paper presents a novel algorithm to estimate the signal probability and switching activity at all nodes in a combinational logic circuit under a zero-delay model without constructing global BDDs. By using Taylor expansion technique, the first-order signal correlation effects due to reconvergent fan-out nodes are taken into account. High accuracy is achieved by considering the dependency of the signal probability and switching activity on each primary input. High speed is also achieved by using the incremental approach for probability calculation. Our approach is able to handle large circuits, since it does not need to construct global BDDs for the probability calculation. The analysis of the time complexity and the experimental results show the running time of our approach to be about 100 times shorter than that of the most accurate approach previously proposed and that our approach has comparable accuracy. The error of the total power estimation is about 0.5% on average.

A floorplanner, FOLM-planner, suitable for SOG gate arrays is presented. FOLM-planner is based on a 'frame overlapping floorplan model, which is free from unnecessary constraints caused by conventional floorplan models, and is easy to use for satisfying timing constraints. FOLM-planner aims at minimizing the net length among frames and controlling frame overlaps for efficient usage of a chip area. To accomplish these objectives, FOLM-planner uses a newly developed force directed method for frame reshaping as well as moving. Experimental results have shown that FOLM layout can shorten the net length inside a frame without the total net length becoming longer.>

This paper describes a resistance calculation program for a layout verification system called EMAP. A new resistance calculation algorithm, based on the finite-element method, and a generalized resistor model, used in this program, are discussed. Contact resistance effects, pinch resistors, and other kinds of resistance appearing in LSI's are considered in the proposed model. The proposed two-dimensional model, in which an inherent three-dimensional structure of resistors is embedded, allows efficient and accurate resistance calculation. The resistance value for an arbitrarily shaped multiregional resistivity and multiport resistor can be calculated efficiently by the proposed algorithm. The algorithm, called direct admittance matrix derivation, makes it possible to eliminate the tedious boundary condition treatment, and provides efficient matrix manipulation. Implementation techniques and related algorithms are discussed; these include resistor recognition from mask artwork, mesh generation for finite elements, node numbering for matrix bandwidth reduction, some properties of matrices appearing in the proposed algorithm, and a circuit representation method for the derived matrices. Some implementation results are also discussed.

A new LSI artwork analysis and processing system, called EMAP, is described with algorithms, a database schema and applications. EMAP provides the designer with the artwork verification and processing tools which include mask artwork processing, geometrical design rule checking, connectivity analysis and electrical circuit parameter calculation. The circuit connectivity data derived from the mask artwork data is used for input to a logic simulator, a timing simulator, a circuit simulator and a circuit schematic generator.