In recent years, the importance of interconnects on top-down engineered lithography-based electronic chips has outrun the importance of transistors as a dominant factor of performance. The major challenges in traditional chips are related to delays of non-scalable global interconnects and reliability in general, which leads to the observation that simple scaling will no longer satisfy performance requirements as feature sizes continue to shrink. In addition, the advent of massive-scale multicore architectures, novel silicon and non-silicon manufacturing techniques (such as self-assembly), and an increasing interest in biological components for computing force us to rethink, re-evaluate, and re-design the communication infrastructure and the communication paradigms in the era of nano- and biotechnology.

In this paper we propose a set of different configurations of failure recovery schemes, developed for network-on-chip (NoC) based systems. These configurations exploit the fact that communication in NoCs tends to be partitioned and eventually localized. The failure recovery approach is based on checkpoint and rollback and is aimed towards fast recovery from system or application level failures. The proposed recovery configurations and partitions of the NoC enhance the performance/overhead of the recovery mechanism. We analyze the effectiveness of these solutions, depending on the traffic characteristics and the expected failure rate.

This paper proposes a method of improving the scalability of checkpoint recovery for network-on-chip based systems in terms of checkpointing latency and memory requirements. The improvement considers the broadcasts implied in the checkpointing protocol. It combines the reduction of the number of broadcasts in the checkpoint synchronization protocol with the use of a more efficient broadcast method at network level.

Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significantly in the near future. The communication requirements of these large Multi Processor SoCs (MP-SoCs) are convened by the emerging network-on-a-chip (NoC) paradigm. In the deep sub-micron (DSM) VLSI processes, it is difficult to guarantee correct fabrication with an acceptable yield without employing design techniques that take into account the intrinsic existence of manufacturing faults. To become a viable alternative IC design methodology the NoC paradigm must address the system-level reliability issues, which is going to be the dominant concern in the DSM and beyond silicon era. By incorporating adaptiveness in the data communication mechanism we are able to tolerate permanent manufacturing faults in the NoC interconnect architectures. The corresponding performance and cost figures must be carefully analyzed and weighted against the specific application requirements. In this paper we explore the performance tradeoffs associated with adaptive routing schemes in NoC fabrics.

Fault-tolerant design of network-on-chip communication architectures requires the addressing of issues pertaining to different elements described at different levels of design abstraction - these may be specific to architecture, interconnection, communication and application issues. Assessing the effectiveness of a particular fault-tolerant implementation can be a challenging task for designers, constrained with tight system performance specifications and other requirements In this paper, we provide a top-down view of fault-tolerance methods for NoC infrastructures, and present a range of metrics used for estimating their quality. We illustrate the use of these metrics by simulating a few simple but realistic fault-tolerant scenarios.

Three dimensional (3D) network on chip (NoC) has attracted researchers' attention recently. 3D NoCs are capable of achieving better system throughput and lower latency compared to the corresponding 2D implementations. To fully exploit the performance benefits of 3D architectures, it is imperative to address signal integrity issues in the design phase and its implications on energy dissipation. In this work we show that by incorporating joint crosstalk avoidance and multiple error correction schemes it is possible to enhance the robustness and reduce the energy dissipation simultaneously for both the 3D and more conventional planar NoC architectures. The achievable energy savings in 3D NoCs is significantly more than that in 2D structures.

Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far. This document outlines the top-level view on a system of benchmarks for networks on chip (NoC), which intends to cover a wide spectrum of NoC design aspects, from application modeling to performance evaluation and post-manufacturing test and reliability. For performance benchmarking, requirements and features are described for application programs, synthetic micro-benchmarks, and abstract benchmark applications. Then, it proposes ways to measure and benchmark reliability, fault tolerance and testability of the on-chip communication fabric. This paper introduces the main concepts and ideas for benchmarking NoCs in a systematic and comparable way. It will be followed up by a report that will define a benchmark framework and the syntax of interfaces for benchmark programs that will allow the community to build-up a benchmark suite

Network-on-chip (NoC) communication fabrics will be increasingly used in many large multicore system-on-chip designs in the near future. A relevant challenge that arises from this trend is that the test costs associated with NoC infrastructures may account for a significant part of the total test budget. In this paper, we present a novel methodology for testing such NoC architectures. The proposed methodology offers a tradeoff between test time and on-chip self-test resources. The fault models used are specific to deep submicrometer technologies and account for crosstalk effects due to interwire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to the components under test in a recursive manner. It exploits the inherent parallelism of the data transport mechanism to reduce the test time and, implicitly, the test cost. We also describe a suitable test-scheduling approach. In this manner, the test methodology developed in this paper is able to reduce the test time significantly as compared to previously proposed solutions, offering speedup factors ranging from 2x to 34x for the NoCs considered for experimental evaluation.

Commercial designs are currently integrating from 10 to 100 embedded functional and storage blocks in a single SoC and the number is likely to increase significantly in the near future. With this ever increasing degree of integration, design of communication architectures for big SoCs is a challenge. The communication requirements of these large multi processor SoCs (MP-SoCs) are convened by the emerging network-on-a-chip (NoC) paradigm. The basic operations of NoC infrastructures are governed by on-chip packet-switched networks. Crosstalk between adjacent wires is an issue in NoC communication fabrics and it can cause timing violations and extra power dissipation. Crosstalk avoidance codes (CACs) can be used to improve signal integrity and also reduce the coupling capacitance and hence the energy dissipation of a wire segment. By incorporating crosstalk avoidance coding (CAC) in NoC data streams we are able to reduce communication energy, which will help to decrease the energy dissipation as a whole

A novel method for on-line fault detection and location in network-on-chip (NoC) communication fabrics is introduced. This approach is able to distinguish between faults in the communication links and faults in the NoC switches. The idea is based on the use of code-disjoint routing elements, combined with parity check encoding for the inter-switch links. We analyze the effect of our method on relevant performance parameters - power, latency, and throughput. Experiments show that our approach is effective and requires minimal modifications of the existing design methods for NoC interconnects.

In this paper, we present a novel built-in self-test methodology for testing the inter-switch links of network-on-chip (NoC) based chips. This methodology uses a high-level fault model that accounts for crosstalk effects due to inter-wire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to its own components under test in a bootstrap manner, and in extensively exploiting the inherent parallelism of the data transport mechanism to reduce the test time and implicitly the test cost

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.

Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs.

Multi-Processor (MP-SoC) platforms are emerging as the latest trend in SoC design. Monolithic bus-based interconnect architectures will not be able to support the clock cycle requirements of these high performance SoCs. Systems having multiple smaller buses, integrated through repeaters or bridges, are possible alternatives. But these kinds of solutions are ad-hoc in nature. By adopting a more structured network-based design paradigm, specific clock cycle requirements can easily be met. The precise focus of this paper is to show how the butterfly fat tree (BFT) can meet this objective when used as the overall MP-SoC interconnect architecture, thereby offering an attractive alternative for SoC interconnect that does not suffer from the non-scalability aspect of the buses in regards to the clock cycle.