This paper briefly outlines the combination of an Agent Based Modeling (ABM) framework for modeling the flow of traffic in an urban center, using a 3D gaming platform and incorporating real world data extracted from cell phone trajectories to guide agent movements. Results are compared against two other sets of real world data. The model validation shows considerable promise both for the simulation itself and the use of cellular location data to infer traffic patterns.

One in four people in a healthcare facility has a pressure ulcer (bedsore) at any given time, and bedsores are one of the leading iatrogenic causes of death reported in developed countries. Standardized documentation is identified as a critical component in the prevention and treatment of pressure ulcers, with the greatest challenges being non-compliance to protocol and inconsistency of documentation. As a result, attention is focused on electronic information systems, and the research objective in this work was to develop an interactive software application on a mobile device (Smartphone; tablet) to allow healthcare workers to electronically document patients' wounds, and to explore whether the application may promote higher consistency and compliance in wound care documentation, and higher patient and caregiver satisfaction relative to paper-based documentation. A prototype application on an Android platform is in progress with additional intelligence over paper-based forms. The prototype is being extended to a version designed as an educational tool for undergraduate nursing students learning clinical practices in wound care. The work advances the emerging area of healthcare applications and supports the increasing prevalence of e-health in nursing practice.

The objective of this paper was to develop an agent-based modeling framework in order to simulate the spread of influenza virus infection on a layout based on a representative hospital emergency department in Winnipeg, Canada. In doing so, the study complements mathematical modeling techniques for disease spread, as well as modeling applications focused on the spread of antibiotic-resistant nosocomial infections in hospitals. Twenty different emergency department scenarios were simulated, with further simulation of four infection control strategies. The agent-based modeling approach represents systems modeling, in which the emergency department was modeled as a collection of agents (patients and healthcare workers) and their individual characteristics, behaviors, and interactions. The framework was coded in C++ using Qt4 libraries running under the Linux operating system. A simple ordinary least squares (OLS) regression was used to analyze the data, in which the percentage of patients that became infected in one day within the simulation was the dependent variable. The results suggest that within the given instance context, patient-oriented infection control policies (alternate treatment streams, masking symptomatic patients) tend to have a larger effect than policies that target healthcare workers. The agent-based modeling framework is a flexible tool that can be made to reflect any given environment; it is also a decision support tool for practitioners and policymakers to assess the relative impact of infection control strategies. The framework illuminates scenarios worthy of further investigation, as well as counterintuitive findings.

No abstract available.

New Rank Theorems for Petri nets are given. These theorems are stronger than the known ones in the sense that the new necessary and sufficient conditions of well-formedness are weaker than the known ones. We show how these theorems can be used in the analysis of workflow procedures.

This paper begins with an overview of several competitive learning algorithms in artificial neural networks, including self-organizing feature maps, focusing on properties of these algorithms important to hardware implementations. We then discuss previously reported digital implementations of these networks. Finally, we report a reconfigurable parallel neurocomputer architecture we have designed using digital signal processing chips and field-programmable gate array devices. Communications are based upon a broadcast network with FPGA-based message preprocessing and postprocessing. A small prototype of this system has been constructed and applied to competitive learning in self-organizing maps. This machine is able to model slowly-varying nonstationary data in real time.

In this paper an improved multiple scan chain testing scheme to enhance stuck-at and delay fault testing is proposed. With judicial selection of taps from an n stage CA generator, correlation within a multiple input scan chain is reduced. Adopting the multiple scan chains fed by the selected taps of the CA generator also eases the difficulty of arranging shift register latches (SRLs) for scan based pseudo-exhaustive stuck-at fault testing.

Fault emulation is a logical extension of current trend of using multiple FPGAs for ASIC emulation. This paper presents the basic infrastructure needed for such an emulator, and discusses the advantages of using a fault emulator as compared to a fault simulator.

In this paper, we present a statistical delay fault estimation technique. The basic method is an extension of STAFAN to include delay faults. A strategy to calculate the transition observabilities of fanout stems is proposed. Correlation within each fanout free region is considered in calculating gate line transition controllabilities. Results show this is a practical method of calculating detectabilities of delay faults. When compared with transition delay fault simulations, the estimations of fault coverage are within 2.3% for the benchmark circuits. Finally, the estimation technique is used to grade delay faults, with comparison to fault simulation results used to validate the method.

Circuit emulation, using dynamically reconfigurable hardware is a high speed alternative to circuit simulation, especially for large and complex designs. Dynamic reconfiguration enhances the ability to efficiently analyze the test of combinational and sequential circuits by providing statistical information on fault grading, detectability, and signature analysis. We present a hardware emulation environment based on dynamically reconfigurable field programmable devices. For this work our main interests are in hardware acceleration of fault simulation in a built-in self-test environment and rapid prototyping of new BIST techniques.>

This paper presents a loop based design scheme suitable for wafer scale systems and introduces a variant of the basic reconfiguration algorithm. The underlying topology has been extended to a nonplanar graph of vertex degree five. The yield for this system is higher than that of a planar graph of vertex degree six and requires less hardware for its implementation. Several comparisons among various topologies and reconfiguration algorithms are made within the context of percolation models.>

An overview of wafer scale systems, including a discussion of yield requirements that could make them viable alternatives for the next generation of computers, is presented. Following this, an architecture necessary in order to fully exploit concurrent processing in an inherently faulty environments such as that envisioned by wafer scale systems is presented. This includes a discussion of exploiting nondeterministic message passing and adaptation for fault and congestion avoidance. The long-term goal of this work is to present a concurrent computer system with emphasis on improving general processing efficiency as opposed to achieving optimal processing upper bounds for specific algorithms.>

A self-pruning binary tree (SPBT) interconnection network architecture that tolerate faults in a wafer scale integration (WSI) environment is proposed. The goal of the SPBT network is to provide a reliable and a quickly reconfigured interconnection network architecture for linear WSI arrays. The proposed architecture uses a bottom-up approach to reconfigure a linear pipelined array on a potentially defective WSI array using a binary tree interconnection scheme. The binary tree is generated by successive formation of hierarchical modules. For N processing elements (PEs) on the wafer, reconfiguration time is O(log N). The propagation delay is bounded by Theta (log N) and is independent of the number of faulty PEs. Faults in the switching network as well as faulty processing elements are tolerated.>

Aliasing estimations for cellular automata (CA) and linear feedback shift registers (LFSR) data compactors are presented. As data compaction is a heavily relied on technique for built-in self-test (BIST) the results should be of practical, as well as theoretical interest. Aliasing estimation techniques for multiple-input data compactors are considered. In particular, exact and approximate computation techniques are developed and discussed for CA and LFSR registers. Aliasing estimates for CA and LFSR structures are provided for the ISCAS-85 benchmark circuits for single stuck-at and single delay faults.>

Relevant signature analysis properties for elementary one-dimensional cellular automata are presented. It is found that cellular automata with cyclic-group rules provide signature analysis properties comparable to the LFSR (linear feedback shift register). A technique of using CALBO (cellular automata-based logic block observation) for both test pattern generation and signature analysis, in a similar manner to a typical BILBO (built-in block observation) implementation, is presented.>

The authors demonstrate that one-dimensional (1-D) cellular automata (CA) form the basis of efficient VLSI architectures for computations involved in the Monte Carlo simulation of the two-dimensional (2-D) Ising model. It is shown that the time-intensive task of importance sampling the Ising configurations is expedited by the inherent parallelism in this approach. The CA architecture further provides a spatially distributed set of pseudorandom numbers that are required in the local nondeterministic decisions at the various sites in the array. The novel approach taken to random-number generation can also be applied to a variety of other highly nondeterministic algorithms from many fields, such as computational geometry, pattern recognition, and artificial intelligence.>

A novel random number generation (RNG) architecture of particular importance in VLSI for fine-grained parallel processing is proposed. It is demonstrated that efficient parallel pseudorandom sequence generation can be accomplished using certain elementary one-dimensional cellular automata (two binary states per site and only nearest-neighbor connections). The pseudorandom numbers appear in parallel from various cells in the cellular automaton on each clock cycle and pass standard empirical random number tests. Applications have been demonstrated in the design and analysis of special-purpose accelerators for Monte Carlo simulation of large intractable systems. In addition, significant advantages in pseudorandom built-in self-test of VLSI circuits using cellular automata based RNGs have been demonstrated.>

A variation on a built-in self-test technique is presented that is based on a distributed pseudorandom number generator derived from a one-dimensional cellular automata (CA) array. The cellular automata-logic-block-observation circuits presented are expected to improve upon conventional design for testability circuitry such as built-in logic-block operation as a direct consequence of reduced cross correlation between the bit streams that are used as inputs to the logic unit under test. Certain types of circuit faults are undetectable using the correlated bit streams produced by a conventional linear-feedback-shift-register (LFSR). It is also noted that CA implementations exhibit data compression properties similar to those of the LFSR and that they display locality and topological regularity, which are important attributes for a very large-scale integration implementation. It is noted that some CAs may be able to generate weighted pseudorandom test patterns. It is also possible that some of the analysis of pseudorandom testing may be more directly applicable to CA-based pseudorandom testing than to LFSR-based schemes.>

The computational complexity measures introduced here are motivated by the trend to higher VLSI integration levels (rather than increased chip area) to accomplish solutions to larger problem instances. It seems that the increase in the computational power of VLSI circuits can be mainly attributed to the reduction in the minimum feature size rather than to an increase in the chip area. In view of this, we present a constant area perspective and consider the discrete Fourier transform and related problems in a VLSI model that has λand T as its resources. Advantages of the mesh algorithm over the shuffle-exchange algorithm in the computation time for the DFT are shown to arise from an upper bound on current density in the wires, which we suggest must be considered in any VLSI grid model.

This correspondence presents a linear systolic array for the implementation pf digital signal processing systems based upon matrix- vector multiplication algorithms where the matrix elements can be computed from their row and column indexes. Haar, Walsh, and the discrete Fourier transforms are solved using this approach. The method presented enables the n2 matrix elements to be computed in situ directly from the 2n matrix indexes. Thus, performance comparable to known systolic matrix-vector multipliers is achieved using only constant I/O bandwidth, rather than O(n) bandwidth required in the more general case. A generalized method is given for the development of recursively formed matrices and specifically the VLSI implementation of the Haar and Walsh transforms.